Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: Micro light emitting diode inspection and repairing equipment including a carrying stage, an optical inspection module and an injection device is provided. The optical inspection module is arranged corresponding to the carrying stage to capture image information and obtain a position coordinate from the image information. The injection device is adapted to move to a target position of the carrying stage according to the position coordinate. The injection device includes a tube and a nozzle. The tube includes a first portion and a second portion connected to the first portion. The extending direction of the first portion is different from the extending direction of the second portion. A fluid blows to the target position after passing through the tube and the nozzle. An inspection and repairing method adopting the micro light emitting diode inspection and repairing equipment is also provided.

Abstract: There is provided a technique that includes: performing a set a plurality of times, the set including: (a) loading at least one substrate into a process container; (b) performing a process of forming a nitride film on the at least one substrate by supplying a film-forming gas to the at least one substrate supported by a support in the process container; (c) unloading the processed at least one substrate from an interior of the process container; and (d) supplying an oxidizing gas into the process container from which the processed at least one substrate has been unloaded so as to oxidize one part of the nitride film formed inside the process container in (b) into an oxide film and maintain another part of the nitride film, which is different from the one part of the nitride film, as it is without oxidizing the another part.

Abstract: This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.

Abstract: An image sensor may include a pixel isolation structure disposed in a semiconductor substrate to define a first pixel region, first and second photoelectric conversion regions disposed in the first pixel region, and a separation structure disposed in the first pixel region, between the first and second photoelectric conversion regions. The pixel isolation structure may include first pixel isolation portions, which are spaced apart from each other in a second direction and extend lengthwise in a first direction, and second pixel isolation portions, which are spaced apart from each other in the first direction and extend lengthwise in the second direction to connect to the first pixel isolation portions. The separation structure may be spaced apart from the pixel isolation structure in the first direction and the second direction, and is at least partly at the same level as the first and second photoelectric conversion regions in a third direction perpendicular to the first direction and the second direction.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A temperature of a pedestal comprising a cooling feature on which a substrate is located is set to less than or equal to 100° C. The substrate is exposed to a plasma treatment to remove chemical residual and/or impurities from features of the substrate including a metal bottom, dielectric sidewalls, and/or a field of dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The plasma treatment may be an oxygen plasma, for example, a direct oxygen plasma. Processing tools and computer readable media for practicing the method are also described.

Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.

Abstract: Provided is a method including at least the thermal treatment step of thermally treating a SOI substrate having a first silicon layer at a first temperature that the diffusion flow rate of an interstitial silicon atom in a silicon single crystal is higher than the diffusion flow rate of an interstitial oxygen atom and the processing step of processing the SOI substrate after the thermal treatment step to obtain a displacement enlarging mechanism.

Abstract: The present disclosure provides a semiconductor manufacturing method and a system therefore. The semiconductor manufacturing method includes: providing a gas from a container through an outlet to a semiconductor wafer manufacturing equipment, wherein a control valve is connected to the outlet to control a gas flow; retrieving a set of parameters corresponding to the gas flow; and determining a nominal position of the control valve by incorporating the set of parameters through a processor in order to provide a desired flow passage into the semiconductor wafer manufacturing equipment, wherein the semiconductor wafer manufacturing equipment includes a plurality of independent reaction chambers, wherein each reaction chamber is individually supplied with a gas pipe, and each gas pipe receives the gas from the container.

Abstract: An integrated chip comprises a substrate, an isolation structure and a gate structure. The isolation structure is disposed in the substrate and enclosing an active region in the substrate. The active region comprises a source region and a drain region separated by a channel region along a first direction. The gate structure is disposed over the channel region and comprising a first gate electrode region and a second gate electrode region arranged one next to another laterally along a second direction perpendicular to the first direction. The first gate electrode region has a first composition, and the second gate electrode region has a second composition different than the first composition.

Abstract: A first regrowth layer and a second regrowth layer comprising GaAs having high resistance are regrown on a surface of an etching stop layer exposed to the bottom of a first groove and a second groove, and then n-type InGaAs is regrown on the first regrowth layer and the second regrowth layer, whereby a source region and a drain region configured to make contact with a channel layer are formed in the first groove and the second groove respectively.

Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

Abstract: The present application discloses a display panel and a manufacturing method therefor, and the method includes steps of: forming a photosensitive element layer, forming a light collimating layer on the photosensitive element layer, and forming an active light-emitting matrix layer on the light collimating layer; where the step of forming the light collimating layer includes: providing a metal substrate, putting the metal substrate into an electrolyte, and preparing a porous oxidized metal as the light collimating layer by a two-step oxidation method.

Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.

Abstract: This application relates to preparation of organic photomultiplication photodetectors, and more particularly to an organic photomultiplication photodetector with bi-directional bias response and a method for producing the same. The photodetector includes an anode layer, an anode modification layer, an interfacial modification layer, an active layer and a cathode layer arranged in sequence. The interfacial modification layer is made of Al2O3. The anode layer is made of indium tin oxide (ITO). The anode modification layer is made of poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)(PEDOT:PSS). The active layer is made of poly(3-hexylthiophene-2,5-diyl):[6,6]-phenyl-C70-butyric acid methyl ester (P3HT:PC70BM). The cathode layer is made of aluminum, silver or gold.