Abstract: Provided is a semiconductor material having improved oxidation resistance. The semiconductor material has a single crystal represented by the following composition formula: Mg2Sn·Zna??Composition formula: in which, a is a Zn content of from 0.05 to 1 at % relative to Mg2Sn.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode and a single field plate. The source electrode, the drain electrode, and the gate electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is between the source and drain electrodes. The single field plate is disposed over the gate electrode and extends toward the drain electrode. The field plate has a first end part, a second end part and the central part. The first and the second end parts are located at substantially the same height. Portions of the central part are in a position lower than that of the first and second end parts, and the first end part extends laterally in a length greater than a width of the gate electrode.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.

Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a WARP value of 3.5 ?m or less, as measured with the back surface of the indium phosphide substrate facing upward.

Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a BOW value of ?2.0 to 2.0 ?m, as measured with the back surface of the indium phosphide substrate facing upward.

Abstract: A method of controlling a scanning-type plasma processing apparatus using a phased array antenna, includes observing light emission of plasma generated inside a processing container through observation windows provided at multiple positions in the processing container, calculating an in-plane distribution of values representing characteristics of the plasma on a substrate, based on data on the observed light emission of the plasma, and correcting a scanning pattern and/or a plasma density distribution of the plasma based on the calculated in-plane distribution of the values representing the characteristics of the plasma on the substrate.

Abstract: A method for manufacturing LED devices is provided. The method comprises forming an epitaxial layer on a starter substrate, the epitaxial layer having a first surface that interfaces with the starter substrate and a second surface opposite to the first surface; establishing an adhesive bond between the second surface of the epitaxial layer and a carrier substrate having a pre-determined light transmittance; etching away the starter substrate; etching away part of the epitaxial layer to form a plurality of light emitting diode (LED) dies on a third surface of the epitaxial layer opposite to the second surface; establishing one or more conductive bonds between selected one or more LED dies, from the plurality of LED dies, and a backplane; weakening the adhesive bond between the second surface of the epitaxial layer and the carrier substrate; and moving the carrier substrate away from the backplane.

Abstract: A method of manufacturing a semiconductor device can include: forming an interlayer dielectric layer on an upper surface of a lower metal layer, the lower metal layer including first and second regions; forming a through hole extending from an upper surface of interlayer dielectric layer to the lower metal layer to expose the upper surface of the lower metal layer; forming a conductive layer covering a bottom part and sidewall parts of the through hole, and the upper surface of the interlayer dielectric layer; forming a first dielectric layer covering the first conductive layer on the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer above the upper surface of the interlayer dielectric layer.

Abstract: A process for producing a chalcogen-containing compound semiconductor includes providing at least one substrate coated with a precursor for the chalcogen-containing compound semiconductor in a process chamber; heat treating the at least one coated substrate in the process chamber, wherein during a heat treatment, a gas atmosphere comprising at least one gaseous chalcogen compound is provided in the process chamber; removing the gas atmosphere present after the heat treatment of the at least one coated substrate as a waste gas from the process chamber; cooling the waste gas in a gas processor, wherein a plurality of gaseous chalcogen compounds-present in the waste gas after the heat treatment of the at least one coated substrate are separated in time and space from one another from the waste gas by respective conversion into a liquid or solid form. Further provided is a device designed to carry out the process.

Abstract: The present application discloses a QLED manufacturing method including: providing a substrate provided with an electron transport layer; depositing a solution on a surface of the electron transport layer, standing until the electron transport layer is infiltrated, and then performing a drying operation, wherein the solution includes a main solvent and a solute dissolved in the main solvent, a polarity of the solute is greater than a polarity of the main solvent, and the solution is not able to dissolve the electron transport material in the electron transport layer; preparing other film layers on the electron transport layer processed by the mixed solvent to prepare the QLED, such that the QLED at least includes: an anode and a cathode arranged oppositely, a quantum dot light emitting layer arranged between the anode and the cathode, and the electron transport layer between the quantum dot light emitting layer and the cathode.

Abstract: A post-processing method of a quantum dot light-emitting diode, which includes the following steps: providing a quantum dot light-emitting diode, the quantum dot light-emitting diode includes a cathode and an anode arranged oppositely, and a quantum dot light-emitting layer arranged between the cathode and the anode; energizing the cathode and anode of the quantum dot light-emitting diode, and performing a light irradiation treatment on the quantum dot light-emitting diode.

Abstract: A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.

Abstract: Methods for forming a semiconductor structure are described. The method includes cleaning a substrate to form a substrate surface substantially free of oxide, exposing the substrate surface to a first molybdenum precursor, and exposing the substrate surface to a reactant to selectively deposit a first molybdenum film on the substrate surface. The method may be performed in a processing chamber without breaking vacuum. The method may also include forming one or more of a cap layer and a liner and annealing the substrate. The method may also include depositing a second molybdenum film on the substrate surface.

Abstract: A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.