Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.

Abstract: Provided is a production method of a SiC wafer which can increase the yield of a SiC wafer which can be prepared from a produced SiC single crystal ingot and the product yield of a semiconductor chip. In forming cylindrical column parts from a SiC single crystal ingot, the diameters of the cylindrical column parts are gradually changed. Specifically, the SiC single crystal ingot configured to have a frustoconical shape is made into, instead of cylindrical column parts all having identical diameters, cylindrical column parts whose diameters increase from the upper surface toward the lower surface of the SiC single crystal ingot.

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

Abstract: A method is provided to fabricate a wafer including a bonding layer interposed between a device wafer and a handle wafer. The method includes performing a first deposition process to deposit an ultraviolet (UV) shield layer on a backside surface of the handle wafer. A second deposition process is performed to deposit a stress compensation layer on an exposed surface of the UV shield layer. The UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer.

Abstract: Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.

Abstract: A reflective mask blank including a substrate, a multilayer reflection film consisting of at least two first layers and at least two second layers that are laminated alternatively and having different optical properties each other, and an absorber film are manufactured by a sputtering method. Each layer is formed by two stages consisting of a first stage applied from when the forming of each layer is started and until a prescribed thickness is formed, and a second stage applied from when the prescribed thickness is formed and until the forming of each layer is completed, and a sputtering pressure of the first stage is set to higher than both a sputtering pressure at which the forming of the layer formed just before is completed, and a sputtering pressure of the second stage.

Abstract: A method of forming an acoustic transducer comprises providing a substrate and depositing a first structural layer on the substrate. The first structural layer is selectively etched to form at least one of an enclosed trench or an enclosed pillar thereon. A second structural layer is deposited on the first structural layer and includes a depression or a bump corresponding to the enclosed trench or pillar, respectively. At least the second structural layer is heated to a temperature above a glass transition temperature of the second structural layer causing the second structural layer to reflow. A diaphragm layer is deposited on the second structural layer such that the diaphragm layer includes at least one of a downward facing corrugation corresponding to the depression or an upward facing corrugation corresponding to the bump. The diaphragm layer is released, thereby forming a diaphragm suspended over the substrate.

Abstract: A cross-couple contact structure is provided that is located on, and physically contacts, a topmost surface of a functional gate structure that is located laterally adjacent to a gate cut region. The cross-couple contact structure extends into the laterally adjacent gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of a first sidewall of a dielectric plug that is present in the gate cut region, and an upper surface of a dielectric liner that is located on a lower portion of the first sidewall of the dielectric plug.

Abstract: The present invention relates to a silicon carbide (SiC) substrate with improved mechanical and electrical characteristics. Furthermore, the invention relates to a method for producing a bulk SiC crystal in a physical vapor transport growth system. The silicon carbide substrate comprises an inner region (102) which constitutes at least 30% of a total surface area of said substrate (100), a ring shaped peripheral region (104) radially surrounding the inner region (102), wherein a mean concentration of a dopant in the inner region (102) differs by at maximum 5·1018 cm?3, preferably 1·1018 cm?3, from the mean concentration of this dopant in the peripheral region (104).

Abstract: The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

Abstract: An apparatus and a method for manufacturing a mask assembly and a method of manufacturing a display device are provided. The apparatus may include: a tensioning part configured to be spaced apart from a mask frame comprising at least one opening, the tensioning part configured to tension a mask sheet in at least one of a first direction and a second direction, the mask sheet comprising a cell area corresponding to the at least one opening, and a dummy portion arranged outside the cell area; a pressing part configured to correspond to the dummy portion and press the dummy portion in a third direction intersecting a plane in which the first direction and the second direction extend; and a header configured to irradiate a laser beam toward the mask sheet to fix the mask sheet to the mask frame.

Abstract: A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device.

Abstract: According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Abstract: A method for surface treatment of an at least primarily crystalline substrate surface of a substrate such that by amorphization of the substrate surface, an amorphous layer is formed at the substrate surface with a thickness d>0 nm of the amorphous layer. This invention also relates to a corresponding device for surface treatment of substrates.

Abstract: The present disclosure provides a method for preparing a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The method includes: forming a first supporting backbone on the substrate; forming a first conductor block on the first supporting backbone; forming a second supporting backbone on the substrate; forming a second conductor block on the second supporting backbone; forming a third conductor block suspended above the substrate and connected to the first conductor block and the second conductor block; sequentially forming an energy removable layer and a capping dielectric layer over the substrate, and the energy removable layer and the capping dielectric layer separating the first conductor block, the second conductor block and the third conductor block; and performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures.

Abstract: An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.