Abstract: A method includes: sandwiching a plastic layer between a glass substrate and a metal plate made of an iron-nickel alloy and joining the metal plate to the glass substrate with the plastic layer in between; forming a mask portion including a plurality of mask holes from the metal plate; joining a surface of the mask portion that is opposite to a surface of the mask portion that is in contact with the plastic layer to a mask frame, which has a higher rigidity than the mask portion and is in a shape of a frame surrounding the mask holes of the mask portion; and peeling off the plastic layer and the glass substrate from the mask portion.

Abstract: Selective ruthenium and selective ruthenium oxide may be used in single damascene processes and/or dual damascene processes to form BEOL metallization layers and vias of an electronic device. A selective ruthenium liner may be formed to achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: A single-crystal ?-Ga2O3 MSM detector and a preparation method thereof, comprising: machining grooves on a single-crystal ?-Ga2O3 substrate using a laser-assisted waterjet machining technique to form a 3D shape; wet etching the machined single-crystal ?-Ga2O3 substrate using an HF solution to remove machining damage; performing Au evaporation on a surface of the single-crystal ?-Ga2O3 substrate after processing, coating an Au thin film on the surface of the single-crystal ?-Ga2O3 substrate; and grinding the surface of the single-crystal ?-Ga2O3 substrate after evaporation to remove the Au thin film on an undressed surface and retain the Au thin film in the grooves, and then obtaining the single-crystal ?-Ga2O3 MSM detector.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further incudes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers.

Abstract: A display device includes a display panel including a flat portion and a bending portion located at a side of the flat portion, an optical film attached on the flat portion of the display panel, and a bending protection layer covering at least a part of the bending portion and contacting one edge of the optical film. The edge of the optical film includes an upper surface, a lower surface and a side surface, the lower surface of the optical film faces an upper surface of the display panel, at least a part of the side surface of the optical film contacts the bending protection layer, and at least a part of the side surface of the optical film protrudes more, as closer to the upper side.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

Abstract: A deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. The deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. To adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. As a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.

Abstract: There is provided a technique that includes: (a) forming a film on a substrate in a process container by performing a cycle a predetermined number of times, the cycle including: supplying an oxygen-containing gas from a pipe made of metal to the substrate in the process container; supplying a nitrogen-and-hydrogen-containing gas from the pipe to the substrate in the process container; and (b) forming a layer on an inner surface of the pipe by supplying a surface treatment gas into the pipe such that the surface treatment gas chemically reacts with the inner surface of the pipe.

Abstract: A deposition mask for making a display device, the deposition mask includes: a frame including a first opening; a first member disposed above the first opening of the frame and including a first portion surrounding at least one second opening and a second portion disposed in the second opening and physically separated from the first portion; and a second member disposed on the first member and including a first connecting portion connected to the frame and a second mesh portion overlapping the second portion.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Abstract: In an apparatus for manufacturing a display device having a mask assembly, the mask assembly includes: a mask frame comprising an opening; a plurality of first supports spaced apart from each other on the mask frame and each comprising a first center portion crossing the opening in a first direction and a first protrusion protruding from the first center portion in a second direction crossing the first direction; a plurality of second supports spaced apart from each other on the mask frame and each comprising a second center portion crossing the opening in a third direction crossing the first direction and a second protrusion protruding from the second center portion in a fourth direction crossing the third direction; and a mask sheet comprising a plurality of pattern holes and arranged over the mask frame to be supported by the plurality of first supports and the plurality of second supports.

Abstract: A method for packaging an integrated circuit chip includes the steps of: a) providing a plurality of dies and a lead frame which includes a plurality of bonding parts each having a die pad, a plurality of leads each having an end region disposed on and connected to the die pad, and a plurality of bumps each disposed on the end region of a respective one of the leads; b) transferring each of the dies to the die pad of a respective one of the bonding parts to permit each of the dies to be flipped on the respective bonding part; and c) hot pressing each of the dies and the die pad of a respective one of the bonding parts to permit each of the dies to be bonded to the bumps of the respective bonding part.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A film forming system for forming a magnetic film is provided. The film forming system includes a processing module configured to form the magnetic film on a substrate, a magnetization characteristic measuring device configured to measure magnetization characteristics of the magnetic film formed on the substrate in the processing module, and a transfer unit configured to transfer the substrate between the processing module and the magnetization characteristic measuring device. The magnetization characteristic measuring device includes a magnetic field applying mechanism having a permanent magnet magnetic circuit configured to apply a magnetic field to the substrate and adjust the magnetic field to be applied to the substrate, and a detector configured to detect magnetization characteristics of the substrate.