Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.

Abstract: An organic light-emitting diode (OLED) deposition system includes two deposition chambers, a transfer chamber between the two deposition chambers, a metrology system having one or more sensors to perform measurements of the workpiece within the transfer chamber, and a control system to cause the system to form an organic light-emitting diode layer stack on the workpiece. Vacuum is maintained around the workpiece while the workpiece is transferred between the two deposition chambers and while retaining the workpiece within the transfer chamber. The control system is configured to cause the two deposition chambers to deposit two layers of organic material onto the workpiece, and to receive a first plurality of measurements of the workpiece in the transfer chamber from the metrology system.

Abstract: A method for nanoparticle fabrication deposits a seed layer of a transparent conductive oxide onto a substrate and deposits a layer of a plasmonic metal onto the transparent conductive oxide layer. The method forms nanoparticles from the deposited metal by transporting the substrate along a transport path and, as the substrate is moving, energizing one or more flash lamps disposed along the transport path to apply a plurality of light pulses that impart a dewetting energy to the deposited metal layer.

Abstract: Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Abstract: A method for structuring a substrate is specified, in particular structuring by means of selective etching in the semiconductor and IC substrate industry, in which the following steps are carried out: providing a substrate, applying a titanium seed layer, full-area coating with a photoresist layer, lithographic structuring of the photoresist layer, in order to expose regions of the titanium seed layer, selectively depositing copper as conductor tracks in those areas in which the titanium seed layer is exposed, removing the structured photoresist, and etching the titanium seed layer in the areas previously covered by the structured photoresist, wherein phosphoric acid is used to etch the titanium seed layer and, in addition, exposure to UV light is carried out during the etching of the titanium.

Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: Disclosed is a semiconductor device manufacturing method, including a preparation step of preparing a laminated body in which a supporting member, a temporary fixation material layer that generates heat upon absorbing light, and a semiconductor member are laminated in this order, and a separation step of irradiating the temporary fixation material layer in the laminated body with incoherent light and thereby separating the semiconductor member from the supporting member.

Abstract: A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.

Abstract: An exemplary plasma processing system includes a plasma processing chamber, an electrode for powering plasma in the plasma processing chamber, a tunable radio frequency (RF) signal generator configured to output a first signal at a first frequency and a second signal at a second frequency. The second frequency is at least 1.1 times the first frequency. The system includes a broadband power amplifier coupled to the tunable RF signal generator, the first frequency and the second frequency being within an operating frequency range of the broadband power amplifier. The output of the broadband power amplifier is coupled to the electrode. The broadband power amplifier is configured to supply, at the output, first power at the first frequency and second power at the second frequency.

Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

Abstract: Single crystal CVD diamond material comprising a total nitrogen concentration of at least 5 ppm and a neutral single substitutional nitrogen. Ns0, to total single substitutional nitrogen, Ns, ratio of at least 0.7. Such a diamond is observed to have a relatively low amount of brown colouration despite the relatively high concentration of nitrogen A method of making the single crystal diamond is also disclosed, the method including growing the CVD diamond in process gases comprising 60 to 200 ppm nitrogen, in addition to a carbon-containing gas, and hydrogen, wherein the ratio of carbon atoms in the carbon-containing gas to hydrogen atoms in the hydrogen gas is 0.5 to 1.5%.

Abstract: A deposition system is provided capable of measuring at least one of the film characteristics (e.g., thickness, resistance, and composition) in the deposition system. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition system in accordance with the present disclosure includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, and a target enclosing the substrate process chamber. A shutter disk including an in-situ measuring device is provided.

Abstract: A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

Abstract: A laminate including a glass plate and a coating layer, wherein the coating layer includes one or more components selected from the group consisting of silicon nitride, titanium oxide, alumina, niobium oxide, zirconia, indium tin oxide, silicon oxide, magnesium fluoride, and calcium fluoride, wherein a ratio (dc/dg) of a thickness dc of the coating layer to a thickness dg of the glass plate is in a range of 0.05×10?3 to 1.2×10?3, and wherein a radius of curvature r1 of the laminate with negating of self-weight deflection is 10 m to 150 m.

Abstract: An apparatus for manufacturing a display device includes a mask assembly, the mask assembly including a silicon substrate having a first surface, a second surface opposite the first surface, and a first opening portion penetrating the first surface and the second surface, and a support substrate on the second surface, the support substrate having a second opening portion connected to the first opening portion. The first opening portion at the first surface is less in width than the first opening portion at the second surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.