Patents Examined by James C. Kerveros
  • Patent number: 10256946
    Abstract: Disclosed is a method for decoding an optical data signal. Said optical data signal is phase and amplitude modulated according to a constellation diagram with at least eight constellation points representing non-binary symbols. Said decoding method comprises the following steps: —carrying out a carrier phase recovery of a received signal ignoring the possible occurrence of phase slips, —decoding said signal after phase recovery, wherein in said decoding, possible cycle slips occurring during phase recovery are modelled as virtual input to an equivalent encoder assumed by the decoding scheme. Further disclosed are a related encoding method as well as a receiver and a transmitter.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 9, 2019
    Assignee: Xieon Networks S.à.r.l.
    Inventor: Stefano Calabro
  • Patent number: 10241866
    Abstract: A method for execution by a processing system in dispersed storage and task network (DSTN) that includes a processor, includes: identifying a slice name of a slice in error of a set of slices stored in a set of dispersed storage (DS) units; identifying a number of slice errors of the set of slices; generating a queue entry that includes the slice name of the slice in error, a rebuilding task indicator, an identity of the set of slices, and the number of slice errors; identifying a rebuilding queue based on the number of slice errors, wherein the rebuilding queue is associated with one of: the set of DS units or another set of DS units; and facilitating storing the queue entry in the identified rebuilding queue.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Adam M. Gray, Wesley B. Leggette, Jason K. Resch, Ilya Volvovski
  • Patent number: 10243586
    Abstract: An encoding method of generating an encoded sequence by performing encoding of a given encoding rate based on a predetermined parity check matrix. The predetermined matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. A parity check polynomial satisfying zero of the LDPC convolutional code is expressible by using a specific mathematical expression.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 26, 2019
    Assignee: SUN PATENT TRUST
    Inventor: Yutaka Murakami
  • Patent number: 10241859
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 10236916
    Abstract: A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventor: Rainer Goettfert
  • Patent number: 10234507
    Abstract: A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer, Phillip A. Senum
  • Patent number: 10229002
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives data object information for a data object and stores the data object information in a dispersed index of a dispersed or distributed storage network (DSN). The computing device also dispersed error encodes the data object to generate sets of encoded data slices (EDSs) (e.g., for data segments of the data object) and updates the index entry state of the dispersed index to moving to indicate that the data object is moving. The computing device distributedly stores the sets of EDSs among a storage units (SUs) of the DSN.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Franco V. Borich, Wesley B. Leggette
  • Patent number: 10222418
    Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 5, 2019
    Assignee: ARM Limited
    Inventors: Yew Keong Chong, Teresa Louise Mclaurin, Richard Slobodnik, Frank David Frederick, Kartikey Jani
  • Patent number: 10218384
    Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Idan Goldenberg, Ishai Ilani, Idan Alrod, Yuri Ryabinin, Yan Dumchin, Mark Fiterman, Ran Zamir
  • Patent number: 10216929
    Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 26, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Benedikt Driessen, Steffen Sonnekalb
  • Patent number: 10211949
    Abstract: Provided is a receiver which includes at least one processor configured to control or execute: a first Bit-Interleaved Coded Modulation (BICM) decoder configured to generate a first output signal corresponding to an upper layer signal by processing a first input signal which includes a superposition coding signal generated at a transmitter by superimposing the upper layer signal and a lower layer signal; a parity generator configured to generate at least one parity based on a result of the processing of the first input signal by the first BICM decoder; and a second BICM decoder configured to generate a second output signal corresponding to the lower layer signal by processing a second input signal which is generated using the parity generated by the parity generator.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-ho Oh, Se-ho Myung
  • Patent number: 10204009
    Abstract: A method of rebuilding data stored as encoded data slices in a dispersed storage network (DSN) includes using a scanning module to identify a slice name of a slice in error of a set of slices stored in a set of dispersed storage (DS) units. The number of erroneous slices in the set of slices is also identified. A queue entry that includes the following items is generated: the slice name of the slice in error; a rebuilding task indicator; an identifier of the set of slices; and the number of slice errors. Additionally, a vault source name is generated based on the number of slice errors. The queue entry is stored in a rebuilding queue at the same or another set of DS units, using the vault source name. A rebuilding module facilitates rebuilding the slice in error.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Adam M. Gray, Wesley B. Leggette, Jason K. Resch, Ilya Volvovski
  • Patent number: 10198315
    Abstract: A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 5, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Idan Alrod
  • Patent number: 10187085
    Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Wei Song, Hao Yang, Fan Zhou, Hou Gang Li, Yufei Li
  • Patent number: 10176886
    Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Seagate Technology LLC
    Inventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner
  • Patent number: 10176040
    Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gerard A. Kreifels
  • Patent number: 10171206
    Abstract: A source device for sending datagrams contained in an aggregated packet structure comprising transport containers each containing one or more datagram segments of the datagram, the source device comprising a feedback processor configured to receive feedback that a transmission of a transport container has failed or a detector unit that detects that a transmission of a transport container will fail; a disassembler unit that disassembles the failed transport container the transmission of which has failed or will fail; a creating unit that creates at least one new transport container from less than all of the failed transport containers without splitting datagrams; and a sending unit that sends sequence information indicating a conversion between a sequence of the transport containers of the failed datagram and a sequence of the transport containers of the new datagram, where the source device is configured to reformat and retransmit datagrams whose transmission has failed.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 1, 2019
    Assignee: Lantiq Israel Ltd.
    Inventors: Daniel Cohn, Yaron Alpert
  • Patent number: 10164656
    Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10162002
    Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, David W. Siljenberg, George R. Zettles, IV
  • Patent number: 10162006
    Abstract: A system and method are provided for boundary scan testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus (SMBus) interface. The drive tester system performs a boundary scan test on the on more digital data storage drives via the standard two-wire interface. The boundary scan test may include a vector test.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: December 25, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Gobinathan Athimolom, Michael Rothberg