Patents Examined by James C. Kerveros
  • Patent number: 10176040
    Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gerard A. Kreifels
  • Patent number: 10176886
    Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Seagate Technology LLC
    Inventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner
  • Patent number: 10171206
    Abstract: A source device for sending datagrams contained in an aggregated packet structure comprising transport containers each containing one or more datagram segments of the datagram, the source device comprising a feedback processor configured to receive feedback that a transmission of a transport container has failed or a detector unit that detects that a transmission of a transport container will fail; a disassembler unit that disassembles the failed transport container the transmission of which has failed or will fail; a creating unit that creates at least one new transport container from less than all of the failed transport containers without splitting datagrams; and a sending unit that sends sequence information indicating a conversion between a sequence of the transport containers of the failed datagram and a sequence of the transport containers of the new datagram, where the source device is configured to reformat and retransmit datagrams whose transmission has failed.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 1, 2019
    Assignee: Lantiq Israel Ltd.
    Inventors: Daniel Cohn, Yaron Alpert
  • Patent number: 10164738
    Abstract: Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Vincent Abayomi Loncke
  • Patent number: 10162006
    Abstract: A system and method are provided for boundary scan testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus (SMBus) interface. The drive tester system performs a boundary scan test on the on more digital data storage drives via the standard two-wire interface. The boundary scan test may include a vector test.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: December 25, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Gobinathan Athimolom, Michael Rothberg
  • Patent number: 10162002
    Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, David W. Siljenberg, George R. Zettles, IV
  • Patent number: 10164656
    Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10157685
    Abstract: A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 18, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae-Kyun Kim, Jin-Hee Cho, Jun-Gi Choi
  • Patent number: 10153055
    Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
  • Patent number: 10141953
    Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 27, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 10142054
    Abstract: A communication unit (2020) performs directly wireless communicates with a portable terminal (3000). A collection information acquisition unit (2040) acquires collection information. A division transmission unit (2060) generates multiple pieces of partial collection information by dividing the collection information, and transmits pieces of partial collection information being different from each other to multiple portable terminals (3000). A redundancy transmission unit (2080) transmits the same collection information to the multiple portable terminals (3000). An index value acquisition unit (2100) acquires any one or two of a reliability index value and a capacity index value of the portable terminal (3000). Based on any one or two of the reliability index value and the capacity index value of each portable terminal (3000), a transmission control unit (2120) selects the division transmission unit (2060) or the redundancy transmission unit (2080) to perform the transmission.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: November 27, 2018
    Assignee: NEC Corporation
    Inventors: Kenichiro Fujiyama, Koji Kida
  • Patent number: 10127112
    Abstract: A method begins by determining to rebuild one or more encoded data slices to a dispersed storage network (DSN) memory unit. The method continues by determining a rebuild rate of the DSN memory unit. The method continues by determining, based on the rebuild rate, a rebuild rate status of the DSN memory unit. The method continues by when the rebuild rate status is a high rebuild rate status, reducing the rebuild rate to the DSN memory unit. The method continues by rebuilding, when the rebuild rate is not zero, the one or more encoded data slices in the DSN memory unit.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10116334
    Abstract: An integrated circuit (IC) includes an encoder circuit. The encoder circuit includes an encoding input configured to receive an input message including one or more data symbols. Each data symbol has N bits and N is a positive integer. The encoder circuit includes an encoding unit configured to perform Reed-Solomon encoding to the one or more data symbols to generate one or more coding symbols. The Reed-Solomon encoding uses a Galois field having an order that is less than 2N. A coded message that includes the one or more data symbols and the one or more coding symbols is provided at an encoding output of the encoder circuit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: October 30, 2018
    Assignee: XILINX, INC.
    Inventor: Hong Qiang Wang
  • Patent number: 10115476
    Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 30, 2018
    Assignee: Apple Inc.
    Inventors: Eyal Gurgi, Yoav Kasorla, Barak Rotbard, Shai Ojalvo
  • Patent number: 10114687
    Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Gilles Ries, Abdelaziz Goulahsen
  • Patent number: 10110350
    Abstract: Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node (10) to a group of destination nodes (21-23), including the steps of marking messages (1) transmitted from the source node (10); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node (10) to the group of destination nodes (21-23) and conclude the presence of an error in the delivery of data.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 23, 2018
    Assignee: Bull SAS
    Inventors: Axel Poudes, Ghassan Chehaibar, Sylvie Lesmanne
  • Patent number: 10089173
    Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 10062427
    Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Whi-Young Bae, Young-Sik Kim, Young-Yong Byun
  • Patent number: 10055285
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • Patent number: 10049763
    Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Lee, Young Jun Ku