Patents Examined by James C. Kerveros
  • Patent number: 10062427
    Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Whi-Young Bae, Young-Sik Kim, Young-Yong Byun
  • Patent number: 10055285
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • Patent number: 10049763
    Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Lee, Young Jun Ku
  • Patent number: 10042577
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by identifying a data object to access within a DSN. The method continues by identifying a vault ID based on the data object. The method continues by obtaining an object ID based on the data object. The method continues by selecting at least one generation ID based on generation status. The method continues, for each generation ID, by generating at least one set of slice names using the vault ID, the generation ID, and the object ID. The method continues, for each set of slice names, by generating a set of slice access requests that includes the set of slice names and accessing the DSN utilizing the set of slice access requests.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wesley B. Leggette, Jason K. Resch, Eric G. Smith, Sebastien Vas, Yogesh R. Vedpathak
  • Patent number: 10031809
    Abstract: A method begins by a dispersed storage (DS) processing module identifying an encoded slice requiring rebuilding. The method continues by the DS processing module determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group determining by the DS processing module whether a valid encoded data slice of the fan-out data slice group is available. When a copy of the encoded data slice of the fan-out encoded data slice group is not available, the method continues by the DS processing module rebuilding the encoded data slice. A storage unit then stores the rebuilt encoded data slice and creates copies of the rebuilt encoded data slice to produce a rebuilt fan-out encoded data slice group.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Asimuddin Kazi
  • Patent number: 10033411
    Abstract: An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventor: Ravi Motwani
  • Patent number: 10020915
    Abstract: An embodiment method includes receiving, by a first user equipment (UE), a message, for a second UE, transmitted over a plurality of resource blocks (RBs) on behalf of a communications controller and determining a plurality of log-likelihood ratios (LLRs) in accordance with the received plurality of RBs. The method also includes transmitting, a subset of the determined LLRs to the second UE.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 10, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yu Cao, Amine Maaref, Mohammadhadi Baligh, Jianglei Ma
  • Patent number: 10013203
    Abstract: A method begins by a dispersed storage (DS) processing module receiving a request to store data in a dispersed storage network and determining dispersed storage error encoding parameters for encoding the data into sets of encoded data slices. The method continues with the DS processing module determining whether the request includes a desired write reliability indication. When the request includes the desired write reliability indication, the method continues with the DS processing module determining whether storage of the sets of encoded data slices is meeting the desired write reliability indication. When storage of a set of encoded data slices is not meeting the desired write reliability indication, the method continues with the DS processing module determining a storage compliance process for the set of encoded data slices to meet the desired write reliability indication and executing the storage compliance process for the set of encoded data slices.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jason K. Resch, Wesley Leggette
  • Patent number: 10013208
    Abstract: According to one mode of implementation it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and optionally on the basis of the values of the data present in the memory the erasure step or the programming step, so doing while optionally using a conventional write command. When the memory is equipped with an error-correcting code based on a Hamming code, a property of the latter makes it possible readily to implement this possible acceleration of the cycles of writings within the memory. This property is that according to which when all the bits of the bytes of a digital word grouping together n bytes are equal to zero, the check bits associated with these bytes are also all equal to zero.
    Type: Grant
    Filed: February 27, 2016
    Date of Patent: July 3, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 10008286
    Abstract: Systems and methods for self-testing archival memory devices are described. The memory device includes a data storage component capable of being coded with data. The memory device further includes a read-write mechanism configured to read, write, and delete data stored on the data storage component. The memory device includes a read-write controller configured to control the read-write mechanism based on input received through a device interface of the memory device, wherein the device interface of the memory device is configured to connect to an external computing device. The memory device further includes a diagnostic controller configured to perform a test on at least one of the data stored on the data storage component, the data storage component, and the read-write mechanism. The memory device includes a power source configured to provide operational power to the diagnostic controller when the memory device is not connected to an external power source.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: June 26, 2018
    Assignee: Elwha LLC
    Inventors: Jeffrey A. Bowers, Peter L. Hagelstein, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Patent number: 9977080
    Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 22, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Ruifeng Guo, Yu Huang, Wu-Tung Cheng
  • Patent number: 9977081
    Abstract: Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: May 22, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Jurgen Serrer, Martin Fischer
  • Patent number: 9972403
    Abstract: Systems and methods for self-testing archival memory devices are described. The memory device includes a data storage component capable of being coded with data. The memory device further includes a read-write mechanism configured to read, write, and delete data stored on the data storage component. The memory device includes a read-write controller configured to control the read-write mechanism based on input received through a device interface of the memory device, wherein the device interface of the memory device is configured to connect to an external computing device. The memory device further includes a diagnostic controller configured to perform a test on at least one of the data stored on the data storage component, the data storage component, and the read-write mechanism. The memory device includes a power source configured to provide operational power to the diagnostic controller when the memory device is not connected to an external power source.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: May 15, 2018
    Assignee: Elwha LLC
    Inventors: Jeffrey A. Bowers, Peter L. Hagelstein, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Patent number: 9941886
    Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.
    Type: Grant
    Filed: August 12, 2017
    Date of Patent: April 10, 2018
    Assignee: Casinda Inc.
    Inventors: Jimmy Yong Xiao, Surendra Kumar Rathaur, Visvamohan Yegnashankaran
  • Patent number: 9927976
    Abstract: A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN) sending a plurality of sets of encoded data slices to DSN memory for storage in accordance with a plurality of sets of DSN data addresses. The method continues with the DS processing module generating retrieval data that is based on a data object number and data storage information. The method continues with the DS processing module dispersed storage error encoding the retrieval data to produce a set of encoded retrieval data slices and generating a set of DSN retrieval data addresses based on the data name and on retrieval data storage information. The method continues with the DS processing module sending the set of encoded retrieval data slices to the DSN memory for storage in accordance with the set of DSN retrieval data addresses.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manish Motwani, Michael Colin Storm, Ilya Volvovski, Greg Dhuse, Andrew Baptist, Wesley Leggette
  • Patent number: 9922725
    Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Bruce Querbach, William K. Lui, David G. Ellis, David J. Zimmerman, Theodore Z. Schoenborn, Christopher W. Hampson, Ifar Wan, Yulan Zhang
  • Patent number: 9916906
    Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 13, 2018
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • Patent number: 9915678
    Abstract: A sensor device for an electronic apparatus is provided with: a sensing structure generating a first detection signal; and a dedicated integrated circuit, connected to the sensing structure, detecting, as a function of the first detection signal, a first event associated to the electronic apparatus and generating a first interrupt signal upon detection of the first event. The dedicated integrated circuit detects the first event as a function of a temporal evolution of the first detection signal, and in particular as a function of values assumed by the first detection signal within one or more successive time windows, and of a relation between these values.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 13, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giuditta Roselli, Michele Tronconi, Fabio Pasolini
  • Patent number: 9906241
    Abstract: An apparatus for a turbo product codes includes a codeword generator and an interleaver. The codeword generator receives a data in a matrix, and generate a turbo product code (TPC) codeword including the data, row parities and column parities. The interleaver interleaves the TPC codeword by assigning at least one bit in at least one row-column intersection of the TPC codeword to at least one master code, and outputs the interleaved TPC codeword.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Lingqi Zeng
  • Patent number: 9881670
    Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 30, 2018
    Assignee: HGST Technologies Santa Ana, Inc.
    Inventors: Anthony Dwayne Weathers, Richard David Barndt, Xinde Hu