Abstract: Provided is a rate matching method and device for a Polar code. The method includes: concatenating K information bits and (N?K) frozen bits to generate a bit sequence of N bits, and encoding the bit sequence of N bits by means of a Polar code encoder with a generator matrix of size N×N to generate an initial bit sequence {S0, S1, . . . , SN?1} of N bits, where K and N are both positive integers and K is less than or equal to N; dividing a circular buffer into q parts, selecting bits from the initial bit sequence {S0, S1, . . . , SN?1} in a non-repeated manner, and writing the bits into the q parts of the circular buffer according to a predefined rule, where q=1, 2, 3 or 4; and sequentially selecting a bit sequence of a specified length from a predefined starting position in a bit sequence in the circular buffer and taking the bit sequence of the specified length as a bit sequence to be transmitted.

Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.

Abstract: Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.

Abstract: Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

Abstract: An encoder includes a first element part and a controller. The first element part includes a first qubit, a second qubit coupleable with the first qubit, a third qubit coupleable with the second qubit, a fourth qubit coupleable with the third qubit, a fifth qubit coupleable with the fourth qubit, a sixth qubit coupleable with the fifth qubit, a seventh qubit coupleable with the sixth qubit, an eighth qubit coupleable with the seventh qubit, and a ninth qubit coupleable with the eighth qubit. The controller is configured to perform a first control. The first control includes encoding a surface code having a code distance of 3.

Abstract: A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

Abstract: The disclosure describes various techniques to control of small angle Mølmer-Sørensen (MS) gates and to handle asymmetric errors. A technique is described for handling asymmetric errors in quantum information processing (QIP) systems. An exemplary method includes implementing a quantum circuit in the QIP system that has first and second qubit lines, with a first qubit state having a greater measurement error than a second qubit state; swapping the roles of the first and second qubit states at a quantum circuit level in response to at least one of the first qubit line and the second qubit line being expected to be at the first qubit state at a measurement; and enabling a quantum simulation using the quantum circuit with the first and second qubit states reassigned in at least one of the first qubit line and the second qubit line after the swapping of the respective roles.

Abstract: A storage device updates optimal parameters associated with a Thermal Region Tag (TRT). A controller on the storage device assigns a TRT to blocks programmed at a given temperature range and updates an optimal TRT parameters by obtaining a set of representative wordlines and a set of indicative wordlines for a block assigned to the TRT. The controller performs a bit error rate (BER) estimation on indicative wordlines in the set until a valid indicative wordline is found. The controller determines whether a BER Estimation Scan (BES) check is to be performed when the valid indicative wordline is found. In performing the BES check, the controller performs the BER estimation on representative wordlines in the set until a valid representative wordline is found. When a valid representative wordline is found, the controller obtains the optimal TRT parameter and updates the optimal TRT parameter.

Abstract: A block storing corrupt data is detected. Based on detecting the block storing corrupt data, threshold voltage (VT) distribution data corresponding to the block is accessed. The VT distribution data comprises one or more VT distribution measurements corresponding to the block. The VT distribution data corresponding to the block is compared with reference VT distribution data. The reference VT distribution data comprises one or more reference VT distributions. Based on a result of the comparison, it is determined whether to perform one or more heroic data recovery processes on the block.

Abstract: A transmission side transmission device includes: a first transmitter including a first switch; and a second transmitter including a second switch. A main signal is input to either the first transmitter or the second transmitter. The main signal input to the first transmitter is a first main signal and the main signal input to the second transmitter is a second main signal. The first transmitter and the second transmitter are configured such that, when the first transmitter detects a fault in the input first main signal: the second transmitter outputs the input second main signal to the first transmitter; and the first transmitter outputs the input second main signal via a first selector.

Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.

Abstract: Systems and methods may ethically evaluate intelligent systems operating in a real-world environment. The systems and methods may generate a clone of the intelligent system, and test the clone in a simulation environment. If the clone passes the testing, the systems and methods may permit the intelligent system to continue operating in the real-world environment. If the clone fails the testing, the systems and methods may override the intelligent system, such as disabling the intelligent system and assuming control in the real-world environment. The systems and methods may be implemented at a hardware level of a data processing device to prevent interference with the systems and methods by the intelligent system.

Abstract: A memory includes: a data receiving circuit suitable for receiving a data during a write operation; a data rotation circuit suitable for changing an order of the data transferred from the data receiving circuit and outputting the data whose order is changed in response to an address during the write operation; an error correction code generation circuit suitable for generating an error correction code based on the data output from the data rotation circuit during the write operation; and a memory core suitable for storing the data received by the data receiving circuit and the error correction code during the write operation.

Abstract: A processing system of a storage network operates by: selecting a queue memory type of a plurality of memory types to store a data object, based on a size parameter associated with the data object; storing the data object in a queue memory device having the queue memory type, when the queue memory type is selected; selecting a main memory type of a plurality of memory types to store the data object, when the queue memory type is not selected; and storing the data object in a main memory device having the main memory type, when the queue memory type is not selected; wherein the data object is dispersed error encoded and stored as a plurality of encoded data slices.

Abstract: A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.

Abstract: This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error correction (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are used, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.

Abstract: This disclosure relates to a network device comprising: a first input interface, a first output interface, and a second output interface, wherein the network device is configured to change from a first state, referred to as a time state, to a second state, referred to as a spatial state, and vice versa, wherein the network device is configured to generate each of a first output message and a second output message based on a first input message, wherein the network device is configured to transmit, in the time state, both, the first output message and the second output message, offset in time either via the first output interface or second output interface, and wherein the network device is configured to transmit, in the spatial state, the first output message via the first output interface and the second output message via the second output interface.

Abstract: A method and apparatus are disclosed for efficient hybrid automatic repeat request (HARQ) process utilization for semi-persistent and dynamic data transmissions, wherein a reserved HARQ process identification (ID) can be reused. A subset of a plurality of HARQ process IDs is reserved to use for a semi-persistent allocation, and data is transmitted based on the semi-persistent allocation. A dynamic allocation is received via a physical downlink control channel (PDCCH). At least one of the reserved HARQ process IDs is selectively used for transmitting data based on the dynamic allocation.

Abstract: A computer implemented method for evaluating autonomous vehicle safety that includes defining criteria for safety of autonomous vehicles in a test space, and dividing the test space into an intended test space and a un-intended test space for the criteria for safety of autonomous vehicles. The intended test space includes characterizations for the autonomous vehicle that can be quantified, and the un-intended test space includes characterizations that are not quantifiable. The method further includes measuring the safety of the autonomous vehicles in the intended test space. The applying the un-intended test space is applied to the intended test space as feedback into the intended test space; and evaluating the intended test space including the feedback from the unintended test space using a combined simulation of peripheral vehicles and autonomous vehicles to provide the evaluation of autonomous vehicle safety.