Patents Examined by James C. Kerveros
  • Patent number: 11327866
    Abstract: A memory test method for being implemented by storing corresponding test result data and test parameter data into memory chips when a burn-in test, a high temperature test, a low temperature test, and a normal temperature test are performed on the memory chips. A memory test method for being implemented by storing the corresponding test result data and the test parameter data into the memory chips after the memory chips finish the burn-in test, the high temperature test, the low temperature test, and the normal temperature test. The memory chips can internally store the test result data and the test parameter data after finishing tests through the memory test method of the present disclosure so that relevant personnel can read data to easily trace back test history of the memory chips.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 10, 2022
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11316536
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: April 26, 2022
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 11309054
    Abstract: A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 19, 2022
    Inventors: Wonyeoung Jung, Hyunglae Eun, Dong Kim, Inhoon Park
  • Patent number: 11295829
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 5, 2022
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 11281603
    Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 22, 2022
    Inventors: Benjamin James Kerr, Philip Rose, Robert Reed
  • Patent number: 11271589
    Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11265023
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 1, 2022
    Inventors: Kyung-joong Kim, Se-ho Myung, Hong-sil Jeong, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 11256568
    Abstract: The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a memory device comprises a memory interface, an ECC generation component, and storage components. The memory interface is configured to receive an access request to an address at which data is stored. The memory interface can also forward responses to the request including the data and ECC information associated with the data. The ECC generation component is configured to automatically establish an address at which the ECC information is stored based upon the receipt of the access request to an address at which data is stored. In one exemplary implementation, the internal establishment of the address at which the ECC information is stored is automatic. The storage components are configured to store the information.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 22, 2022
    Assignee: Nvidia Corporation
    Inventors: Bruce Lam, Alok Gupta, David G. Reed, Barry Wagner
  • Patent number: 11232725
    Abstract: A display device includes a panel unit including a display unit, a first circuit board connected to the display unit, and a first connecting member connected to the first circuit board, an input unit including a connection member configured to attach to the first connecting member, and to provide an image signal to the panel unit, a master configured to output a transmitting signal for diagnosing an electrical connection between the first connecting member and the connection member, a transmitting line connected to the master, an inspecting line configured to connect to the transmitting line through the connection member, and a slave configured to connect to the master through the inspecting line, to receive the transmitting signal as a receiving signal, and to enable determination of on-time duty and off-time duty of the receiving signal to determine whether a connection error between the panel unit and the input unit exists.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 25, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kee Yong Kim
  • Patent number: 11226861
    Abstract: The disclosed computer-implemented method for distributing information across failure domains in servers may include (1) dividing, at a computing device, each of a quantity of “K” failure domains (FDs) in a plurality of FDs into a quantity of “P” portions, where the “K” FDs in the plurality of FDs are constituent parts of respective servers in a plurality of servers, “P” is less than “K,” and “P” is a sum of a quantity of “M” data portions and a quantity of “N” parity portions, (2) creating a quantity of “K” erasure-coded volumes in the “K” FDs, where each erasure-coded volume includes “M” data portions and “N” parity portions, and each portion in each erasure-coded volume is stored in a different FD and (3) combining the “K” volumes to create a file system. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 18, 2022
    Assignee: Veritas Technologies LLC
    Inventors: Anindya Banerjee, Shailesh Marathe
  • Patent number: 11218175
    Abstract: Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: January 4, 2022
    Assignee: Quantum Corporation
    Inventor: George Saliba
  • Patent number: 11218174
    Abstract: Provided are methods and systems for storing data using locally repairable multiple encoding. A data storage method may include generating n N×M encoding matrices, each including an M×M first matrix, an 1×M second matrix in which all of elements have a value of 1, and an M×M third matrix that is a symmetric matrix in which respective columns are configured by changing a sequence of elements from an element set; arranging the encoding matrices into a plurality of groups; generating a data block through the first matrix, a local parity block through the second matrix, and a global parity block through the third matrix by encoding source data of a first group with a first encoding matrix among the encoding matrices arranged into the first group; and merging the global parity block with a global parity block of a second encoding matrix that is different than the first encoding matrix.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignees: Naver Corporation, Industry-University Cooperation Foundation Hanyang University Erica Campus
    Inventors: Chanyoung Park, Jiwoong Won, Junhee Ryu, Kyungtae Kang, Yun-cheol Choo, Sung-Won Jun, Taewoong Kim
  • Patent number: 11210011
    Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Ramin Ghodsi
  • Patent number: 11204828
    Abstract: Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 11187749
    Abstract: A test equipment is provided for over the air tests on a device under test, in particular a user equipment, having a shielded space, at least one signal antenna for transmitting and receiving cellular signals arranged in the shielded space, and a plurality of noise antennas arranged in the shielded space linked in an array configured to create Additive White Gaussian Noise. The noise antennas are equally distributed in three dimensions within the shielded space. Further, a method for testing a device under test is shown.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 30, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Adrian Cardalda-Garcia, Bledar Karajani, Niels Petrovic, Edwin Menzel, Heinz Mellein, Johannes Koebele, Jochen Oster, Vincent Abadie, Jens Wappler
  • Patent number: 11184027
    Abstract: Disclosed are a method and an encoder for performing polar coding on an input data sequence to generate a polar code. The encoding method including: generating, based on a first order index set, a second order index set for parent code length of the polar code, each order index of the first or second order index set representing a priority order of transmitting an information bit in a bit position indicated by the order index relative to transmitting information bits at bit positions indicated by other indexes; spreading, according to the second order index set, the input data sequence to a data sequence with bit number equal to the parent code length; performing polar coding on the spread data sequence to generate the polar code.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 23, 2021
    Assignee: NTT DOCOMO, INC.
    Inventors: Runxin Wang, Chongning Na, Mingyuan Yang, Yousuke Sano, Satoshi Nagata
  • Patent number: 11182243
    Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDPC) decoding of codewords of failed word lines is performed with the updated soft information.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Fan Zhang
  • Patent number: 11175984
    Abstract: This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are use, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 16, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Craig Robertson, Mike Jadon
  • Patent number: 11172191
    Abstract: An imaging device includes a first memory configured to perform writing to multiple addresses thereof by designating the multiple addresses on address-by-address basis, a second memory configured to perform writing simultaneously to multiple address thereof, and a control circuit that controls readout of signals from the first memory and the second memory. The control circuit is configured to perform a first operation mode to sequentially designate the multiple addresses of the first memory and sequentially perform readout of signals from the multiple addresses of the first memory, and a second operation mode to sequentially designate the multiple addresses of the second memory and sequentially perform readout of signals from the multiple addresses of the second memory so that an output value from the second memory becomes the same as a value expected as an output value from the first memory in the first operation mode.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 9, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinya Nakano
  • Patent number: 11165439
    Abstract: A syndrome-based decoding method and apparatus for a block turbo code are disclosed. An embodiment of the present invention provides a syndrome-based decoding method for a block turbo code that includes an extended Hamming code as a component code, where the decoding method includes: (a) generating an input information value for a next half iteration by using channel passage information and the extrinsic information and reliability factor of a previous half iteration; (b) generating a hard decision word by way of a hard decision of the input information value; (c) calculating an n number of 1-bit syndromes, which corresponds to the number of columns or rows of the block turbo code, by using the hard decision word; and (d) determining whether or not to proceed with the next half iteration by using the calculated n number of 1-bit syndromes.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 2, 2021
    Inventors: Jun Heo, Byungkyu Ahn, Sung Sik Yoon