Abstract: A method comprises executing a testing operation on a plurality of redundant components of an edge device. In one example, based, at least in part, on the testing operation, at least one redundant component of the plurality of redundant components is identified as having an operational issue, and the at least one redundant component is deactivated in response to the identifying. One or more remaining redundant components of the plurality of redundant components are utilized in one or more operations following the testing operation.

Abstract: An information processing device according to the present invention includes: a memory; and at least one processor coupled to the memory. The processor performing operations. The operations includes: constructing second data that is acquired, based on first data containing a plurality of observation values in a plurality of times, by stacking the first data with respect to the times, and extracting a constant pattern that is a combination of the observation values having temporal constancy in the first data, based on the second data; generating a difference between the first data and the constant pattern in the time; and extracting a random pattern that is a combination of the observation values without temporal constancy, based on the difference.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

Abstract: A memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.

Abstract: A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for: selecting error-prone pages each having a number of errors, which exceeds a threshold, among the plurality of pages, based on the number of errors of each of the plurality of pages; ranking the error-prone pages based on the numbers of errors therein; and performing a test read operation on the error-prone pages based on the ranking.

Abstract: A computer implemented method for evaluating autonomous vehicle safety that includes defining criteria for safety of autonomous vehicles in a test space, and dividing the test space into an intended test space and a un-intended test space for the criteria for safety of autonomous vehicles. The intended test space includes characterizations for the autonomous vehicle that can be quantified, and the un-intended test space includes characterizations that are not quantifiable. The method further includes measuring the safety of the autonomous vehicles in the intended test space. The applying the un-intended test space is applied to the intended test space as feedback into the intended test space; and evaluating the intended test space including the feedback from the unintended test space using a combined simulation of peripheral vehicles and autonomous vehicles to provide the evaluation of autonomous vehicle safety.

Abstract: Systems, devices, media, and methods are presented for releasing an application feature in incremental stages while monitoring the application for anomalies. The feature includes a package of code and an action setting. The methods in some implementations include identifying active devices on which the application has been installed, monitoring the application according to a set of metrics, activating the feature by changing its action setting for a first segment of the active devices, pausing the feature if an anomaly is detected among the set of metrics, and generating a repair ticket. As long as no anomaly is detected, the activating step proceeds for subsequent segments of the active devices, iteratively, until the release is completed. A feature rank may be used to process and release a plurality of features in order of priority.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each including a plurality of memory cells coupled to a plurality of word lines, and a controller configured to determine an operation status regarding a selected memory block among the plurality of memory blocks by performing read test operations to the selected memory block in stages. During the read test operations, the controller adjusts the numbers of word lines selected in each of the stages, based on an error.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: The present disclosure relates to a detection system including a control circuit, a power line network bridge circuit, a fixture device and a detection device. The control circuit is configured to generate a plurality of detection signals. The power line network bridge circuit receives detection signals through a power line. The fixture device is electrically connected to the power line through the power line network bridge, and is configured to receive the detection signals. The fixture device is configured to transmit the detection signals to a device under test, so that the device under test displays a plurality of media. The detection device is configured to capture the media and transmit the media to the control circuit. The control circuit is further configured to determine whether the media match with detection parameters.

Abstract: System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Abstract: Method and system for predicting failures in interconnected systems based on quantum computing is disclosed. The method may include identifying a set of unique patterns from input data received from a plurality of input data sources, determining a correlation between at least two input data sources, creating a plurality of sets of clusters corresponding to the plurality of input data sources based on the correlation, extracting data associated with each of the set of unique patterns based on the plurality of sets of clusters, predicting, based on the extracted data, a failure of at least one interconnected system using a trained ML model, processing the extracted data associated with each of the set of unique patterns and information associated with the predicted failure through a quantum computing layer, and generating, through the quantum computing layer, at least one corrective action for the at least one interconnected system.

Abstract: A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

Abstract: A method for application operational monitoring may include an operational monitoring computer program: (1) ingesting a plurality of service level indicator (SLI) metrics for an application, each SLI metric identifying a number of successful observations and a number of total observations; (2) calculating a SLI score for each SLI metric based on the number of successful observations and the number of total observations for the SLI metric; (3) weighting the SLI score for each SLI metric; (4) combining the weighted SLI scores into an application SLI score; (5) calculating a calculated error budget based on the application SLI score; (6) determining that the calculated error budget exceeds an error budget for the application; (7) generating a notification in response to the calculated error budget breaching the error budget; and (8) causing implementation of a restriction on the application, wherein the restriction prevents enhancements to the application.

Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.

Abstract: The voter circuit and method determines a voted output among plural inputs each carrying circular data. To supply the voted output, a statistical average (e.g., mean or median) is computed by grouping the plural inputs into pairs, and for each pair generating a minimum angular difference by selecting the minimum of (a) the absolute difference between the pairs of inputs, and (b) the conjugate of the absolute difference between the pairs of inputs. The voted output is a statistical average generated from the minimum angular difference.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.

Abstract: Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.