Patents Examined by James Peikari
  • Patent number: 7373459
    Abstract: A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of the request inputted from the client terminal, a first Uniform Resource Identifier (URI) check step of, when it is determined that the request contents is cacheable in the method check step, checking a URI included in the request from the client terminal to determine whether the request contents is cacheable or uncacheable, a first URI hash search step of, when it is determined that the request contents is cacheable based on determination of the first URI check step, searching a URI hash to determine to execute any of regular caching, priority caching and access limitationing operation, and a step of executing any of the regular caching, priority caching and access limitationing operation according to determination in the first URI hash search step.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: May 13, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Aoki, Takashi Nishikado, Daisuke Yokota, Yasuhiro Takahashi, Fumio Noda, Yoshiteru Takeshima
  • Patent number: 7370084
    Abstract: Dynamic access is provided to automation resources, where, in a distributed automation system having a plurality of automation components, a first automation component searching for an automation resource sends a request to the automation system and, for this request, receives a response regarding availability of suitable automation resources from all automation components which it has been possible to reach, and then selects that automation component which has the suitable automation resource and uses the automation resource.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: May 6, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Clemens Dinges, Michael Schlereth
  • Patent number: 7359276
    Abstract: An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: April 15, 2008
    Assignee: Xilinx, Inc.
    Inventors: Robert D. Turney, Paul R. Schumacher, Kornelis Antonius Vissers
  • Patent number: 7356730
    Abstract: A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 8, 2008
    Assignee: Adaptec, Inc.
    Inventors: Thomas R. Ulrich, James R. Schweitzer, Gregory D. Bolstad, Jay G. Randall, John R. Staub, George W. Priester
  • Patent number: 7356661
    Abstract: An information recording/reproduction apparatus according to one aspect of this invention includes a first recording/reproduction unit configured to execute recording, reproduction, and deletion of information for a built-in first recording medium, a second recording/reproduction unit configured to execute recording and reproduction of information for a detachable second recording medium, a recording control unit configured to control to record a library information file, that contains a plurality of pieces of library information corresponding to a plurality of contents information recorded on the first and second recording media, on the first recording medium, and a deletion control unit configured to execute a process for deleting all pieces of library information contained in the library information file, and a process for deleting all pieces of contents information recorded on the first recording medium.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: April 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Nakashika
  • Patent number: 7356734
    Abstract: A method and apparatus for data backup is disclosed in which prior to actually performing a backup operation from a subscriber computer, the backup server device checks a specified server to determine if parts of the subscriber data to be backed up can be backed up or replicated from data on the specified server. If it can, the backup server uses that specified server to create a backup of the subscriber data to be backed up. If it cannot, then the data is backed up from the subscriber computer.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: April 8, 2008
    Assignee: CenterBeam, Inc.
    Inventors: Glenn Ricart, Marc Epstein, Sheldon Laube
  • Patent number: 7353325
    Abstract: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: April 1, 2008
    Assignee: SanDisk Corporation
    Inventors: Karl M. J. Lofgren, Robert D. Norman, Gregory B. Thelin, Anil Gupta
  • Patent number: 7353329
    Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Robert M. Ellis, Kuljit S. Bains, Chris B. Freeman, John B. Halbert, Narendra S. Khandekar, Michael W. Williams
  • Patent number: 7350018
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: March 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
  • Patent number: 7346738
    Abstract: An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: March 18, 2008
    Assignee: Broadband Royalty Corp.
    Inventor: Robert C Duzett
  • Patent number: 7346805
    Abstract: A method for storing data includes writing the data to a temporary storage location and buffering a mirror request to copy the data from the temporary storage location to a mirror. Once all the data is present, the validity of the data is determined. If the data is valid, the mirror request is executed. Otherwise, the mirror request is deleted.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: March 18, 2008
    Assignee: EMC Corporation
    Inventors: Michael Scharland, Arieh Don, Alexandr Veprinsky
  • Patent number: 7343448
    Abstract: A storage system includes a cache device that has a cache memory as a high-speed-access storage medium, a disk device that has a disk as a high-capacity storage medium, and a control device that accepts an access request from a client device and makes the cache device and the disk device execute a process corresponding to the access request. The cache device, the disk device, and the control device are decentralized on a network.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: March 11, 2008
    Assignee: Fujitsu Limited
    Inventors: Takashi Watanabe, Kazuichi Ooe
  • Patent number: 7340639
    Abstract: A system and method proxies data access commands across a cluster interconnect between storage appliances in a cluster. Each storage appliance activates two ports for data access, a local port for data access requests directed to clients of the storage appliance and a proxy port for data access requests directed to the partner storage appliance. Clients utilizing multi-pathing software may send data access requests to either the local port of the storage appliance or the proxy port of the storage appliance. The system and method improve high availability especially during a loss of connectivity due to non-storage appliance hardware failure.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 4, 2008
    Assignee: Network Appliance, Inc.
    Inventors: Herman Lee, Vijayan Rajan
  • Patent number: 7337171
    Abstract: A logically-partitioned computer system provides support for multiple logical partitions to access a single file system, thereby allowing the logical partitions to share a file without the overhead of communicating over a VLAN. An area of shared memory is defined that multiple logical partitions may access. One or more file control blocks that control access to the files in the file system are then created in the shared memory. Existing mechanisms for locking a file system between processes may then be used across logical partitions to serialize access to the file system by all processes in all logical partitions that share the file system. In this manner the sharing of files in a file system is enabled by leveraging existing technology that is used within a single logical partition to extend across multiple logical partitions.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: David Joseph Gimpl, Thomas Marcus McBride, Tammy Lynn Van Hove
  • Patent number: 7337296
    Abstract: A method for use in a computer. A user of the computer stores a table of selections in a permanent memory structure of the computer, each selection indicating a memory object and one of at least two memory management policies for the memory object. The selections may select from one or more choices: e.g., whether pages of the memory object are to be reserved, or faulted on demand; whether pages of the memory object are to be locked into physical memory of the computer, or to be demand paged from a fluid page pool; whether pages allocated for the memory object are to be zeroed; whether the memory object is to be mapped using shared page tables; or specifying whether memory for the memory object is to be allocated contiguous physical pages of memory. A symbolic name is assigned to each of the memory objects. A non-privileged process issues a request designating one of the memory objects by symbolic name, and allocating memory from a reserved pool of memory for use in the object.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 26, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Karen Lee Noel, Nitin Y. Karkhanis
  • Patent number: 7334155
    Abstract: A storage control apparatus and a storage control method are provided wherein in a system having a plurality of disk systems and secondary disk systems at remote sites, the data transfer amount between a central processing unit and a disk system can be reduced when duplicate disk write is performed, the performance can be prevented from being degraded even if the distance between control units is elongated, and the intermediate results of a transaction are not left. A standard time is determined and a program is provided which instructs a secondary central processing unit to reflect only update information having a write time older than the standard time, upon a logical disk in the secondary disk system.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 19, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Ninose, Hiroshi Arakawa, Yoshihiro Asaka, Yusuke Hirakawa
  • Patent number: 7330949
    Abstract: A method is adopted in a control apparatus for controlling ID information stored in a storage medium in conjunction with a terminal for reading the ID information from the storage medium and used to catalog information for the storage medium into a memory employed in the control apparatus. In an operation to catalog information into the memory of the control apparatus, the terminal receives the information, reads the ID information from the storage medium and transmits the information and the ID information to the control apparatus and the control apparatus catalogs the information and the ID information in the memory by associating the information with the ID information.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takaragi, Chikashi Okamoto
  • Patent number: 7330957
    Abstract: A management server includes the user management segment information having stored therein a volume managed by a user, a receiving unit for receiving a volume allocation request from a management computer, a sending unit for sending the volume allocation request to a storage system and an updating unit for updating the user management segment information based on the information on the allocated volume received from the storage system. The storage system includes a unit for receiving the volume allocation request from the management server, and based on the volume allocation request, allocating the volume from the unallocated volume that can be allocated by all the users.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: February 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Fumi Miyazaki, Masayasu Asano, Yasunori Kaneda
  • Patent number: 7330936
    Abstract: A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: February 12, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Thang M. Tran, Muralidharan S. Chinnakonda, Rajinder P. Singh
  • Patent number: 7330938
    Abstract: System and method for a hybrid-cache. Data received from a data source is cached within a static cache as stable data. The static cache is a cache having a fixed size. Portions of the stable data within the static cache are evicted to a dynamic cache when the static cache becomes full. The dynamic cache is a cache having a dynamic size. The evicted portions of the stable cache are enrolled into the dynamic cache as soft data.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: February 12, 2008
    Assignee: SAP AG
    Inventors: IIiyan N. Nenov, Panayot M. Dobrikov