Abstract: An apparatus and a method for updating data in an embedded system are provided. The apparatus includes a processor for retrieving new data and a transmission line. The transmission line connects to the processor to receive the new data and transmits the new data to the embedded system. The data of a data area has a end address for the data and a plurality of application programs arranged in order, and the new data includes an application program update.

Abstract: A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is typically a separate device that is tied to a specific chip select line and/or address range of a system, whereas synchronous Flash memory generally can be placed in any available memory slot and assigned one of several possible chip selects and address ranges. This lack of predictability makes installing a boot memory based on a non-volatile synchronous memory device difficult. A synchronous Flash boot memory device of the detailed invention is adapted to identify itself and its chip select/address range to the memory controller at power up, reset, or upon receiving an identification request. This allows the utilization of the detailed synchronous Flash memory as a boot memory in synchronous systems where a reserved boot memory slot and/or chip select are not provided.

Abstract: A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to the target storage system; causing the host to access the volume on the drive to be migrated through an input/output port of the drive to be migrated as the external volume of the target storage system; blocking the other input/output port of the drive to be migrated while maintaining the access to the external volume of the target storage system; reconnecting the blocked input/output port with an interface in the target storage system; blocking the input/output port through which the external volume is being accessed, and connecting it with the interface in the target storage system; and implementing the drive to be migrated in the target storage system.

Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.

Abstract: Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format.

Abstract: A method for storing data received from a host processor at a primary storage subsystem in a data storage system includes writing the data to a first volatile cache memory in the primary storage subsystem and copying the data from the primary storage subsystem to a secondary storage subsystem. The second subsystem writes the copied data to a second volatile cache memory and returns an acknowledgment to the primary storage subsystem responsively to writing the copied data to the second volatile cache memory and prior to saving the data in the second non-volatile storage media. The primary storage subsystem signals the host processor that the data have been stored in the data storage system responsively to the acknowledgment from the secondary storage subsystem.

Abstract: In a distributed system, a server may distribute a primary object copy having one or more chunks of data associated with a primary per-chunk metadata copy to a client over a network. The client may selectively fetch and update the one or more chunks of data of the primary object copy based on the primary per-chunk metadata copy. For example, by determining at a client whether a portion of the data in a cached data object, such as a file, is changed relative to a copy of a data object for the cached data object at a server, less than all of the data of the cached data object may be replaced with a corresponding data in the copy of the data object.

Abstract: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area.

Abstract: A recording medium stores data supplied from an external device. A memory stores an erase program for executing erasing of the data stored in the recording medium. An erasing unit erases the data stored in the recording medium in accordance with the erase program stored in the memory, in accordance with a start instruction for instructing a start of erasing the data supplied from the external device.

Abstract: Duplicate data are stored in separate storage units SU(0) 16 and the SU(1) 26, respectively. The storage area in each of the SU(0) 16 and the SU(1) 26 is divided into master storage regions and sub storage regions each of which is allocated alternately to the storage units SU(0) 16 and SU(1) 26 in increments of fixed addresses. The store request is issued to both of the storage units SU(0) 16 and SU(1) 26 allocated the master storage region and the sub storage region, and the fetch request is issued to one of the storage units SU(0) 16 and SU(1) 26 allocated the master storage region from the RSC(0) 34 and RSC(1) 44.

Abstract: A memory architecture allows for use of non-addressable NAND memory to be used as boot memory in digital processing systems. NAND memory, which is typically of lower cost and higher density, may displace all memory in processor systems, as particularly useful in low-power processor implementations. During commencement of a boot sequence, a preselected address is provided to a NAND flash memory. This preselected address coincides with that expected by a processor unit during commencement of a boot sequence. Upon completion of a selected duration, the NAND flash increments to a next, sequential memory location and thus outputs a sequence of instructions on its data lines. The data lines of the NAND flash memory are provided as input data lines to a processor unit. The processor unit, during a boot sequence, fetches subsequent boot instructions at a timing that coincides with that which is output from the NAND flash memory.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: Methods and systems for operating automotive computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which critical data, e.g. the object store, can be maintained in the event of a power loss. Circuitry is provided to ensure that the SRAM receives back up power from the battery at appropriate times. Software manages the SRAM and the other storage assembly components and makes use of virtual paging or virtual addressing techniques to keep track of where various pages, including object store pages, are stored in the system. The software knows where all of the object store pages are located so that in the event of a power loss, the page locations are known and hence the pages can be used when power is restored.

Abstract: A storage server uses a semantic processor to parse and respond to client requests. A direct execution parser in the semantic processor parses an input stream, comprising client storage server requests, according to a defined grammar. A semantic processor execution engine capable of manipulating data (e.g., data movement, mathematical, and logical operations) executes microcode segments in response to requests from the direct execution parser in order to perform the client-requested operations. The resulting operational efficiency allows an entire storage server to be collapsed in some embodiments into a few relatively small integrated circuits that can be placed on a media device's printed circuit board, with the semantic processor itself drawing perhaps a few Watts of power.

Abstract: Techniques for utilizing a time-to-live timeout on a logical connection to a resource (e.g., a database) from a cache are provided. When a logical connection to the resource is obtained, a timeout is set specifying the amount of time the logical connection can be utilized. If the timeout expires, the logical connection is closed and the underlying physical connection can be returned to the cache.

Abstract: A content addressable memory includes a plurality of CAM blocks, each including an array of CAM cells to store a predetermined range of data values, a parsing circuit having an input to receive the search key and having an output to provide a selected portion of the search key in response to a select signal, and a plurality of block select circuits, each configured to enable a corresponding CAM block if the selected portion of the search key falls within the predetermined range of data values for the corresponding CAM block.

Abstract: A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the storage system. This storage system includes channel adapters, disk drives, disk adapters, and network switches. Further, the front side cache memories connected with the channel adapters and the back side cache memories connected with the disk adapters are provided as two layered cache system. When a request for writing data is given to the storage system by the host computer, the data is written in both the front side cache memory and the back side cache memory. The write data is duplicated by placing the write data in one of the front side cache memories and one of the back side cache memories or two of the back side cache memories.

Abstract: An HDD is divided into a segment area storing multimedia data, an information file area storing an information file of a file, and a system information area storing a system information file. Storage of the system information file in the system information area and storage of the information file in the information file area are performed every prescribed time (X seconds), instead of a time point when recording and/or reproduction is stopped. If an apparatus suddenly stops, a location where damage is likely in the HDD can be detected by referring to the information file area and the system information area.

Abstract: A technique includes writing blocks of data from a plurality of servers to an array of disks that are shared in common by the servers. Prior to the writing in each block of data to the array of disks, the method includes storing in a journal a copy of the block of data to be written to the array of disks. Also stored in the journal is at least one header, and this header(s) indicates that the copy was successfully stored in the journal.

Abstract: A disk drive control system comprising a micro-controller, a micro-controller cache system adapted to store micro-controller data for access by the micro-controller, a buffer manager adapted to provide the micro-controller cache system with micro-controller requested data stored in a remote memory, and a cache demand circuit adapted to: a) receive a memory address and a memory access signal, and b) cause the micro-controller cache system to fetch data from the remote memory via the buffer manager based on the received memory address and memory access signal prior to a micro-controller request.