Abstract: A CMOS random access memory has storage elements (1, 2 and 3) which produce complementary outputs on a pair of output conductors (7, 8). In order to speed up the establishment of the output voltages on the conductors two cross-connected transistors (22, 23) are provided to supplement the discharging of that conductor which is to have the lower voltage, each transistor being responsive to the voltage on one conductor to discharge the other conductor. The correct timing of the operation of the cross-connected transistors is provided by two further transistors (26, 27) having their gates respectively connected to the conductors which are arranged to become conducting when an adequate voltage charge has been achieved by the storage element. When either of the further transistors conducts a transistor (24) in series with the two cross-connected transistors is turned on to enable them to operate.

Abstract: 44Gate potentials of transistors Q.sub.R0 and Q.sub.R1 provided in an active pull-up circuit APo are always controlled to be appropriate values by a clock signal .phi..sub.p. As a result, reverse flow of electric charge from a capacitor C.sub.R0 or C.sub.R1 to a bit line LB or BL can be prevented and unfavorable influence due to such reverse flow of electric charge can be avoided in operation of the active pull-up circuit APo.

Abstract: A programmable matrix has improved programming circuitry which allows the matrix to be programmed without raising the output terminals or power supply to higher than normal voltage levels. The circuitry includes a bidirectional output buffer and a multi-purpose input pin. The output buffer is provided with a control input and at least one buffer output. A switching device in the buffer provides a path to ground for programming current when a programming enable signal is applied to the control input and a concurrent operating level voltage pulse is applied to a selected buffer output. Programming current may be supplied via a dedicated input pin, but is preferably supplied via the multi-purpose input pin. A higher than normal operating voltage signal applied to the multi-purpose input pin acts to produce the programming enable signal which is subsequently applied to the buffer control input.

Abstract: An arrangement for purging a magnetic bubble memory and providing a visible purge verification utilizes the thermal compensation Z-axis coil for providing a purge field. A power supply, purge switch and current sensitive circuit interrupter are connected across the thermal compensation coil. When the switch is closed, a surge of relatively high current many times greater than that required for thermal compensation is applied to the coil. Accordingly, the bubbles in the memory will completely disappear. The circuit interrupter is used to halt the purge current once it exceeds the required purge value. This protects the thermal compensation winding and also provides a visual verification that a purge pulse has occurred.

Abstract: A magnetic bubble memory system with a write protecting function is disclosed. In a power on reset mode or initiallizing mode of an information handling system including the bubble memory system, a bubble memory controller directs to and stores in its own memory, an information representative of a write protecting range for a bubble memory device, from a hidden memory region of the bubble memory device. The bubble memory controller compares the write protecting range to the information designating the address range of the bubble memory device in which a new information is to be written, in response to the write command from a host central processing unit. As a result of the comparison, if the both address ranges overlap each other, the bubble memory controller will execute the write protection and generate a write protection error message for the host CPU.

Abstract: An asynchronous semiconductor memory device having an address change detector which generates a pulse with a specified pulse width by detecting change in an address signal and a component for holding an internal circuit in the non-operating condition responding to the address signal for a period when said pulse does not exist. The internal circuit is caused not to operate in response to an unwanted address signal generated in the course of the change of the address signal input from an external device, or in response to an unwanted address signal generated by noise. Thereby power consumption is reduced.

Abstract: Herein disclosed is a bipolar memory having redundancy, which can be produced with a small area. In this semiconductor memory having a body memory for storing data and a spare memory for relief of fault bit of the body memory, a row is selected by cutting fuses in a decoder. Fundamentally signal lines such as word lines are not provided with fuses. Other parts including a power source and a reference voltage source are provided with fuses without decreasing the operating speed accompanied by only a slight increase in the area.

Abstract: Optical devices using an organic charge transfer salt as the switching and storage media are disclosed. Generally, a light beam of a given intensity directed to a film of certain organic charge transfer salts causes the illuminated area to change from a first to a second state. This electrochemical process is reversible with heat energy transforming the illuminated area back into the first state. The first and second states have identifiably different optical and electrical properties. The organic charge transfer salt is used to fabricate an erasable or permanent optical memory and a threshold on bistable optoelectronic switch.

Abstract: In a Bloch-line memory wherein a magnetic film comprises a first and a second major line and a minor loop portion defined between the first and second major lines, successive presence and absence of magnetic bubbles being transferred along the first major line in response to a plurality of information signals, the information signals being memorized as vertical Bloch line pairs in domain walls of stripe-domains generated in the minor loop portion, the memorized vertical Bloch line pairs being propagated towards the second major line and being read out as bubbles into the second major line, the magnetic film is formed with a plurality of endless long grooves at desired locations in the minor loop portion and an endless stripe-domain is generated and stabilized in each endless long groove, so that the propagation of vertical Bloch line pairs can be performed step by step.

Abstract: A magnetic bubble memory device comprises a magnetic bubble memory chip, a unit for generating a bias field, a magnetic shield, and a unit for compensating the bias field, wherein the thermodependency of the bias field is compensated to approximate that of the operation characteristics of the memory chip over a wide temperature range, thereby providing a wide region in which operation is ensured.

Abstract: A digital memory based on a memory cell having two magnetoresistive ferromagnetic film portions separated by an intermediate layer all of which are gradually narrowed at the ends thereof.Adjacent memory cells are preferrably arranged in a line with conductive junctions therebetween. The magnetic state of each cell can be sensed or set by providing currents of different magnitudes in conductive word lines which overlie the cells. The narrowed ends of the cells reduce demagnetizing effects which occur if the cell ends are abruptly terminated.

Abstract: A magnetic bubble memory chip is disposed at a position surrounded by a rectangular annular core having two pairs of opposite sides wound by a pair of wires, respectively, and is covered by a case for confining revolving magnetic field, thereby providing a revolving magnetic field to said chip. A bubble memory includes a permament magnet used as a holding magnetic field source, lying at a predetermined angle to the chip. An inclination between the chip and the magnet is provided on the revolving-magnetic-field confining case to be inserted between the chip and the magnet by having the case changed in plate thickness.

Abstract: Apparatus and methods are disclosed for providing an increased flexibility and rate in processing data in a random access memory (RAM) system. The apparatus comprises, in a first embodiment, a switching circuit which is coupled to the word lines of the RAM array and which is selectively operable in two modes. The switching circuit operates in a first mode to transmit word line signals to a single row of memory cells in the RAM array in accordance with principles well known in the prior art. The switching circuit is responsive to a control circuit, and operates in a second mode to alter, along the row of memory cells in the RAM array, the word line signal path, to provide simultaneous accessing of portions of at least two adjacent rows of memory cells in the RAM array. Such simultaneous accessing allows the processing of more data through the memory system that was previously possible in accordance with principles known in the prior art.

Abstract: A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode which has dual control gates disposed thereon. Each control gate includes a layer of dual electron injector structure (DEIS) and a polysilicon gate. When writing a "0" from the volatile storage capacitor to the floating gate, one of the control gates removes charge from the floating gate. To write a "1", the other control gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical. In order to minimize the adverse effects of process variations, the gate electrode of the word line device is electrically in common with one of the control gates.

Abstract: A CMOS array is described where the memory cells are formed in n-type wells. No back biasing is employed. To prevent generation of minority carriers within the wells, on-chip filtering of power used for the devices in the wells and for biasing the wells is employed. Other techniques are used to reduce problems associated with minority carrier generation.

Abstract: An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.

Abstract: A static MOS RAM cell is provided that is resistant to inadvertent change of state due to charged particles striking the cell without decreasing write time. First and second cross-coupled transistors are coupled between first and second nodes, respectively, and a first voltage. First and second loads are coupled between the first and second nodes, respectively, and a second voltage. A first coupling transistor is coupled between the first node and a first input terminal, and has a gate coupled for receiving a write signal. A second coupling transistor is coupled between the second node and a second input terminal, and has a gate coupled for receiving the write signal. First and second variable loads are coupled between the first node and a gate of the second latching transistor, and the second node and a gate of the first latching transistor, respectively, for providing a resistance in the standby mode and relatively no resistance in the write mode.

Abstract: An FET read only memory cell circuit is disclosed wherein word lines serve to augment the precharging of the bit lines. If an FET read only memory site is preprogrammed as a binary one, for example, then when its word line is pulsed, the bit line will be insured to have an affirmatively high potential, representing a binary one state. This improves the reliability of the operation of the circuit by minimizing the effects of charge leakage from the bit line.

Abstract: An emitter coupled logic circuit includes a bypass circuit which provides a conductive path for current when a programmable fuse is blown, so that input data is transmitted independently of the state of a clock signal. In one implementation, the circuit takes a register configuration having a master section and a slave section, each incorporating a programmable fuse. When the fuse in just one section is intact, the circuit serves as a clocked latch. When both fuses are blown, the bypass circuit is enabled so that the register functions as a combinatorial circuit which produces an output signal dependent on the input signal without reference to a clock signal.

Abstract: A redundant type memory circuit having a normal memory cell array, a first decoder circuit for operatively accessing normal array, a redundant memory cell array, a second decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder circuit at a first delay period when no faulty cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.