Abstract: A non-volatile random access memory (NVRAM) cell including a volatile static type random access memory cell consisting of a flop-flip circuit having two nodes on which a paired bit signal are accessed and a non-volatile electrically erasable programmable read-only memory (EEPROM) cell consisting of a memory transistor having a floating gate, a capacitor circuit, on which a voltage called as a writing voltage is applied, including a tunnel capacitor, and two transistors for determining the polarity of the charge being to be stored at the floating gate with a tunnel current in the tunnel capacitor corresponding to the level of the bit signal existing at one of the two nodes in the flip-flop circuit. When the power supply voltage of the NVRAM cell is turned off, the EEPROM cell stores the positive or negative charge at the floating gate corresponding to the bit signal level at the node in the flip-flop circuit holding the charge after the power supply voltage and the writing voltage are turned off.

Abstract: A magneto-optical recording medium is disclosed in which a magnetic thin film recording layer is formed by a magnetic material having a Curie temperature or magnetic compensation temperature as low as 50.degree. to 250.degree. C. and a coercive force as large as 1 KOe or more and having an easy axis of magnetization perpendicularly to the film surface. A substantially transparent magnetic material film layer of ferrite, garnet or the like is disposed adjacent the recording film layer, large in the Faraday rotation angle and having an easy axis of magnetization perpendicularly to the film surface. A transparent substrate is disposed on the side of incidence of light. The substantially transparent magnetic material layer of the ferrite, garnet or the like may increase the magneto-optical rotation angle in the magnetic thin film recording layer, or may increase the magneto-optical rotation angle by the Faraday effect.

Abstract: A magnetic bubble memory device comprises a bubble propagation path defined by a wide-gap pattern. This bubble propagation pattern has a geometry which is favorable for gaining an increase in density and which can provide a high propagation characteristic.

Abstract: A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer, at least one memory cell having a capacitor for storing charges of an amount corresponding to a logic value and a first transistor having source and drain regions formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor, a first drive circuit for applying a voltage to the gate of the first transistor through a word line, a second drive circuit for selectively applying a voltage of one of first and second levels through a bit line and the first transistor to the capacitor, and a bias circuit for applying a voltage to the substrate. The first transistor of the memory device is a p-channel transistor formed in the n-type semiconductor layer which is formed in the surface area of a p-type semiconductor layer. The bias circuit includes a charge pump section for setting the potential of the substrate at a third level lower than the first voltage.

Abstract: A magnetic bubble memory module having a rectangular core shaped like a picture frame providing windings on respective two pairs of opposite sides, at least one magnetic bubble memory chip disposed in an area surrounded by the core, a flexible substrate having a chip-loading section for loading the magnetic bubble memory chip thereon and having four corners for leading out lead wires connecting signal lines and driving lines of the chip. A revolving magnetic field-confining case accommodates the core, the chip and the flexible substrate and enables the lead wires of the flexible substrate at the corners of the chip-loading section to be drawn out therethrough.

Abstract: A semiconductor memory device provided with first and second bit lines, each of which is connected to a memory cell comprising a nonvolatile transistor and a dummy cell comprising a nonvolatile transistor. The first and second bit lines are respectively connected to high voltage generators which are applied at the time of data programming. At the time of data reading, data-detecting and storing means comprising a flip-flop circuit detects data, while amplifying a potential difference between the first and second bit lines. At the time of data writing, the data detecting and storing means temporarily stores data in accordance with the contents of externally supplied writing data. A first switching transistor is provided between the first data input-output node of the data-detecting and storing means and the first bit line. The second switching transistor is connected between the second data input-output node of the data-detecting and storing means and second bit line.

Abstract: A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged. The memory cell is comprised of transistors (M1, M2, M3, M4) connected to each other and to a supply voltage (Vcc) to thereby form a cross-coupled inverter storage device. Transistors (M5, M6) are connected to diode transistor (M7) and between the cross-coupled inverter (M1, M2, M3, M4) and column lines (54, 56) to thereby form and XOR gate on said column lines (54, 56) and diode transistor (M7). The diode transistor is connected between transistors (M5, M6), ROW line (50) and MATCH line (52), such that during CAM matches the diode transistor allows charge to be siphoned from MATCH line ( 52) and during a write to said CAM cell allows charge to build up.

Abstract: A semiconductor memory device having a PROM with an output register has an initialize input terminal and a programmable initial data memory cell for each bit. When an initialize input signal is supplied to the initialize input terminal, the output register is cleared or present in accordance with the content of the initial data memory cell, whereby the reduction of adaptability caused by a decrease in input terminals can be prevented, a circuit arrangement can be simplified, and a high degree of integration and high-speed operation can be achieved.

Abstract: A bubble generator for use in a bubble memory device combines a nucleating generator and replicating generator in a unified structure with first and second hairpins disposed at respective first and second regions to define nucleation and replication sites. The conductor layer is configured such that the same polarity of current flow causes magnetic fields of opposite sense at the nucleation and replication sites. The nucleation site is used only to generate the seed bubble required at the replication site. Once the seed bubble is present, the replication site is utilized to produce the data stream. The nucleation and replication sites are preferably spaced apart with a propagation track extending from the former to the latter, and the first and second hairpins are series-connected with the series connection crossing the propagation path. The hairpins are preferably directed oppositely so that when the rotating field is in the right phase for replication, it is 180.degree. out of phase for nucleation.

Abstract: A bias magnet for a bubble memory device is comprised of a single material low permeability magnet contoured to enhance the magnetic field in the central area of the magnet and is adapted to be slightly larger than the bubble memory chip and in thermal contact therewith, the entire bubble memory chip and bias magnet structure to be surrounded by the rotating magnetic field drive coil structure.

Abstract: A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

Abstract: Stabilization of the propagation of storage bits around the storage loops of a Vertical Bloch Line (VBL) memory is obtained by the vapor-deposition of a nickel-iron film over the VBL structure. The film has a composition range of 65-90% nickel and a thickness of 1,000 to 10,000 Angstroms, and is deposited in a vacuum of 10.sup.-4 to 10.sup.-6 Torr to provide parallel, periodic, magnetic stripe domains, and thus potential well domains, that have a periodicity in the range of 0.1 to 1 micron. The stripe domains are oriented perpendicular to the direction of data propagation and form potential wells along the elongated direction of the storage loops.

Abstract: A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

Abstract: A circuit arrangement comprises a matrix-shaped memory for variably adjustable delay of digital signals, whereby trigger elements in the form of two inverters fed back to one another are provided as storage elements, one of the two nodes thereof being connectible to a write bit line by way of a switching transistor controllable from a write word line and the other being connectible to a read bit line via a switching transistor controllable from a read word line. A row selector is clocked by the input data clock and is continuously settable and resettable at any time, the row selector comprising two signal outputs per selection stage which are offset in phase relative to one another, these respectively selecting one of the write word lines or read word lines which are provided per row of the matrix-shaped memory. Two separate bit lines, namely a write bit line and a read bit line are provided per column, these being respectively interconnected to all memory cells of a column.

Abstract: A magnetic bubble memory has the longitudinal direction of a minor loop, i.e. a row of permalloy patterns, on a magnetic film of a (111) crystal plane aligned with the [110] crystal axis of the magnetic film. By aligning the direction of bubble transfer in the minor loop with the [110] crystal axis, the bias magnetic field margin, .DELTA.H.sub.B, is enabled to increase and the strength of the holding magnetic field, H.sub.DC, is enabled to decrease.

Abstract: In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.

Abstract: The semiconductor memory device includes an internal refresh circuit and an input circuit composed of first and second transistors of a different conductivity type having gates connected in common to an external control signal input terminal and connected in series with each other. A third transistor is connected in series to the first and second transistors. The third transistor is deactivated when the internal refresh circuit, operates to carry out a self-refresh mode, thereby suppressing a power consumption in the input circuit.

Abstract: A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle sequences, each store cycle sequence having a (HIV) high-voltage timing signal during a first interval, and first and second store timing signals. The memory cell circuit also has a recall cycle. Each recall cycle has a memory reset signal to pre-set the state of the memory cell circuit during a first interval, a recall output signal at a predetermined voltage level and a recall transfer signal. The memory cell comprises a volatile RAM cell having a flip-flop providing an output signal at an output terminal. The flip-flop also has a RESET TERMINAL responsive to a reset signal for forcing the flip-flop to assume a predetermined state in response to the memory reset signal and a SET TERMINAL responsive to a set signal for setting the state of the volatile RAM cell in a recall sequence.

Abstract: A memory integrated circuit component comprises: a memory; addressing circuitry for the memory; and, power switch circuit, programmable to either: (a) electrically couple or decouple the addressing circuitry and a power supply selectively in accordance with an enable signal; or, (b) maintain the addressing circuitry electrically coupled to the power supply independent of the enable signal.With such arrangement, an integrated circuit component manufacturer avoids having to produce two separate types of non-volatile integrated circuit memories (i.e., a power switched component and a non-power switched component), but rather such manufacturer is able to fabricate a common non-volatile integrated circuit memory component which may be programmed after fabrication by either the user or the manufacturer as either a non-power switched memory component or a power switched memory component.

Abstract: An electronic device, such as a bubble memory (21), which has a narrow temperature band of operation, is maintained within the narrow temperature band by a Peltier circuit (30). The Peltier circuit (30) includes a Peltier junction (31) which is placed in a heat conducting relationship with the bubble memory (21). The Peltier circuit (30) has the advantage of being able to alternately heat or chill the bubble memory device (21) in order to maintain the bubble memory device (21) within its recommended temperature range.