Abstract: A redundant type memory circuit having a normal memory cell array, a first decoder circuit for operatively accessing normal array, a redundant memory cell array, a second decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder circuit at a first delay period when no faulty cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.

Abstract: A magnetoresistive random access memory array and signal processing system which provides an improved signal to noise ratio. The basic memory complex associated with the storage of a single binary digit is a quad of memory elements or cells which are addressed in complementary fashion. The enhanced read-out signal discrimination is had by utilizing a double-correlated double-sampling differential signal processing system in which complementary data is serially passed through the same path with repeated high-speed differencing which greatly reduces nonuniformity fixed patterns as well as correlated low frequency temporal noise.

Abstract: In order to facilitate a test of the operations of a semiconductor memory device, the semiconductor memory device includes a line selection checking unit coupled to a cell matrix and column gates to form a logic gate circuit unit consisting of a plurality of transistors, the gates of the transistors being connected to word lines or bit lines. The line selection checking unit has a voltage or current detection portion connected to a pad for detecting an output voltage or current of the line selection checking unit.

Abstract: The bubble memory comprises a magnetic layer in which the magnetic bubble can move under the action of a rotary field, a deposited pattern formed from a high permeability magnetic material and separated from the magnetic layer by an electrical insulating layer, a U-shaped electric conductor placed between the magnetic layer and the deposited pattern and electrically insulated therefrom, the deposited pattern covering the base of the internal space defined by the electric conductor and thus defining a nucleation position. The generator also comprises an implanted pattern produced in a fraction of the thickness of the magnetic layer, the implanted pattern at least covering the nucleation position.

Abstract: A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory's normal sense amplifiers and the memory's data input and output buffers. The secondary sense amplifiers are connected to selected ones of the sense amplifiers in accordance with a first predefined subset of the memory's column address signals. A decoder circuit, which is directly responsive to a second predefined subset of the column address signals, selects one of the secondary sense amplifiers and connects it to the memory's data input and output buffers. Since the decoder is directly responsive to the second predefined subset of the column address signals and does not need to latch in new address values after the detection of an address signal transition, all the secondary sense amplifiers can be accessed much faster than the other data storage locations in the memory.

Abstract: A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

Abstract: An electrically erasable programmable semiconductor memory cell having an associated conducting column line, read/write line, sense line and row line includes a floating gate transistor which controls the discharge of the read/write line to the column line during read cycles. During write cycles and precharging of said read/write line the column line is made electrically floating so that a faster precharge time and hence access time is obtained and so that access time is independent on the conducting state of the floating gate transistor resulting at commencement of a read cycle.

Abstract: A dynamic semiconductor memory comprising memory cells each including a pair of complementary bit lines, a storage capacitor and a device for selecting that capacitor. The memory further comprises a sense amplifier and a control device, and a greater differential voltage can be obtained from these bit lines by varying the ratio of their floating capacitance. Thus, the conventional requirement for balancing the complementary bit lines is eliminated and the lines can be formed in a multi-layer structure. This contributes significantly to making the memory cell areas smaller.

Abstract: A memory device has memory cells, first latches and second latches which latch storage data from the memory cells accessed in response to a row address signal, a read circuit for reading out the contents of the first and second latches, and a control circuit for controlling the operation of the above components. In order to increase a read rate of the memory device, the read circuit alternately reads the contents of the first latches and the second latches. While the read circuit is reading out the contents of the first latches, the second latches latch the storage data of the memory cells of the next row to be selected in response to the next address signal. While the contents of the second latches are being read out, the first latches latch the storage data of the memory cells designated by the next row address signal.

Abstract: The static random access memory reduces the access time thereof and reduces the power consumption thereof during its time of operation, and employs a circuit arrangement such that not only is the logical amplitude of each bit line diminished during a read-out operation, but the bit line is precharged after a write operation is accomplished during a write operation.

Abstract: A current steering differential write circuit is provided that creates a narrow write pulse width without affecting the read threshold of a memory array. The memory array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of current drain lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. A word line driver circuit is coupled between the first voltage terminal and one of the word lines of each of the rows for selectively applying voltage to the one of the word lines. A current drain circuit is coupled between one of the current drain lines of each of the rows and the second voltage terminal for sinking current from the one of the current drain lines. A sense amplifier is coupled to the bit lines of each of the columns for sensing current in the bit lines. A decoder circuit is coupled to the bit lines for enabling current through the bit lines.

Abstract: An improved semiconductor memory, suitable for a video system, includes a memory cell array, a first access circuit operatively performing a write operation and a read operation to the memory cell array, and a second access circuit operatively performing a read operation to the memory cell array in response to different groups of address signals from those applied to the first access circuit. The two access circuits can operate asynchronously and can simultaneously access the memory.

Abstract: A semiconductor memory device includes: a semiconductor memory which is driven in response to a power source voltage supplied between a power source pad and a ground pad; and a peripheral circuit for executing the readout of data from and the writing of the same in this semiconductor memory. The power source pad is divided into a main power source pad and a back-up power source pad. The peripheral circuit is made operative by a voltage applied between the main power source pad and ground pad. The semiconductor memory is made operative by a main power source voltage which is applied to the main power source pad and is supplied through a first diode, or by a back-up power source voltage which is applied to the back-up power source pad and is supplied through a second diode.

Abstract: A magnetic bubble memory module containing a magnetic bubble memory device and its analog peripheral circuits mounted on a substrate, having outer input/output lead terminals, allowing the module to be mounted on a conventional printed circuit board instantaneously with other electronic elements. Lead terminals of the magnetic bubble memory device are protected by a protection means of an insulator such as plastic material, so that the magnetic bubble memory device is protected from the electrostatic discharge damage caused by the touching of a charged body such as human fingers. This results in high reliability and high production yield of the magnetic bubble memory apparatus.

Abstract: In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.

Abstract: A semiconductor memory device in which the selected word line is energized only during a limited period of time is disclosed. The memory device is equipped with a clock generator which generates a one-shot pulse signal in response to a change in address signal or to an application of a write-enable signal, and the selected word line is energized by the one-shot clock signal. The clock generator further generates a one-shot clock signal in response to a change in an input data signal in a data-write operation. The input data is thereby sorted into the accessed memory cell, even when the data to be stored is supplied a relatively long time after the write-enable signal is applied.

Abstract: A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

Abstract: A circuit for writing bipolar memory cells is provided that reduces power dissipation by requiring only a small voltage change on the bit lines between read and write modes. The memory circuit includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between the first voltage terminal and one of the word lines of each of the rows for selectively applying voltage to the one of the word lines. A decoder circuit is coupled to the bit lines for enabling current through the bit lines.

Abstract: A register sub-circuit for a logic system is described which is capable of loading a logic signal from a bus, holding the state of the logic signal, and dumping the logic signal onto a precharged high capacitance bus. The circuit is master/slave in operation permitting the register to simultaneously dump the current contents of the register at the same time a new value is being loaded into the register. The circuit operates with a single phase clock. The circuit is easily integratable. The circuit comprises a storage sub-circuit and one or more dump sub-circuits. The circuit presents a low capacitance load to the dump control line.

Abstract: A magnetic device comprising a first and a second plate of a magnetic material between which domains are situated. An interaction force occurs between the domains in the two plates. Stable domain positions in a second plate define equally stable domain positions in a first plate. One or both plates can be provided with domain guiding structures. Domain displacement in one plate can control a domain displacement in the other so that a variation in the interaction force is produced.