Abstract: A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer.

Abstract: An improved nonvolatile memory has an adaptive system to regulate the charging current supplied to store data on nonvolatile storage nodes in order to provide acceptability low strain on the tunnel oxide and to compensate for process variations and change in the Fowler-Nordheim tunnel oxide transport characteristics caused by electron trapping over time.

Abstract: Static random access memory having an edge-triggered power up architecture. Each element of the signal path is powered up only during the period when it is expected to be active. Separate delays are provided to tailor the delay of the power-up pulses for each separate circuit component, and separate 1-shot pulse generators, with the pulse width tailored to the power-up duration required by each circuit element, are provided for each circuit element.

Abstract: A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to produce a voltage pattern that has one high node and one low node (72, 74) for a normal cell and two intermediate voltage nodes for a shorted cell. A following logic circuit (76) responds to the voltage pattern to produce an output voltage that has one value when the cell is functioning correctly and another value when the cell is shorted.

Abstract: A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct write mode, and characterized by its absence of read disturb. In one form of its practice, the floating gate is divided into three regions situated with relation to specified regions in the substrate. The first region of the floating gate is dielectrically isolated from a conductively doped region in the substrate so as to form a capacitor; the second region is similarly situated, but forms a significantly smaller capacitor and utilizes a dielectric suitable for Fowler-Nordheim tunneling or Poole-Frenkel conduction of charge therethrough; and the third region overlaps a channel of a field effect type sense transistor, conduction through which is responsive to the charge resident on the floating gate.

Abstract: A dynamic memory obtains reduced leakage currents through the access transistors by preventing the low-going column conductors from reaching zero volts for at least a majority of the duration of the active portion of a memory cycle. The low-going conductors are allowed to reach zero volts during the refresh operation. One advantage is a possible increase in the data storage time between required refresh operations. An increase in the refresh interval is especially useful for memory operations wherein a multiplicity of columns are selected for a given row selection. The present technique also addresses the tendency toward increased sub-threshold leakage as field effect transistor thresholds decrease.

Abstract: A nonvolatile semiconductor memory circuit is provided with a plurality of bit lines and a plurality of word lines. The nonvolatile semiconductor memory cells are located at intersections of the bit lines and word lines and formed by MOS transistors having a floating gate and a control gate therein. A bias circuit supplies a read-out voltage to the control gate of the selected nonvolatile semiconductor memory cell. Sense amplifiers are also included, each having an input which receives read-out data from the selected nonvolatile semiconductor memory cell, and an output which outputs amplified read-out data.A bias circuit is formed by a dummy cell having the same construction as the nonvolatile semiconductor memory cells. A dummy sense amplifier is included having the same construction as the sense amplifiers. A voltage setting circuit is also included, having feedback circuitry connected between the output of the voltage setting circuit and the control gate of the MOS transistor in the dummy cell.

Abstract: A dynamic random access memory device is equipped with a test circuit for testing an internal refresh circuit. In a test mode, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated. Further, data is written into the designated memory cell from outside of the memory device, and the data stored in the designated memory cell is then read out to check whether the read-out signal is coincident with the written data.

Abstract: An I.sup.2 L programmable read only memory (PROM) output circuit has a selectable dual non-inverting input differential amplifier with each non-inverting input connected to a different column of memory elements. In the read mode the circuit operates at very low power levels and down to 1 volt. To program the memory elements, the circuit includes two selectable programming current sources which self extinguish as soon as the memory element being programmed changes from its unprogrammed to its programmed state. Switching between the read and program modes is accomplished merely by changing the voltage on the B+ terminal; 1-3 volts for read and 9-12 volts for program.

Abstract: Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines.

Abstract: A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed within a single memory clock cycle via separate volatile and non-volatile bit lines. The cell stores volatile data by the storage of charge on a dynamic storage capacitor formed of a semiconductor device and stores non-volatile data by the storage of charge in the floating gate of a transistor. An array of the memory cells illustrates comparison of the volatile and non-volatile data elements within a single memory cycle particularly suited for pattern recognition.

Abstract: An information recording method is provided, in which a p- or n-type semiconductor wafer is irradiated with an energetic particle beam such as an electron beam thereby to control, e.g., decreased or increased generation of the surface photovoltage at the irradiated area so that information may be recorded on the wafer.

Abstract: A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the gate to source voltage of the detector transistor (36) equal to the approximate threshold voltage of the transistor. The drain of the detector transistor (36) gates an amplifier transistor (30) which inhibits or passes a read signal (18) to the gate of a digit line pull down transistor (32) which provides an active pull down on a digit line (26) that is precharged to a high voltage prior to a memory read cycle.

Abstract: A memory apparatus has a dummy cell comprising two sets of series connections of MOS transistors and capacitors, respectively, connected to a pair of bit lines, which are connected to a sense amplifier of a flip-flop type, and a third MOS transistor having a source and a drain thereof connected between junction points of the MOS transistors and the capacitors of the dummy cell. The capacitors are charged at a high level potential and a low level potential, respectively, of the bit lines and then they are shorted to each other through the third MOS transistor so that they have a common potential of a middle potential level. The potential of the middle level can be supplied to a pair of input terminals to the flip-flop type sense amplifier as a reference potential signal. Thus, it is possible to assure a stable sensing operation by the sense amplifier which is free from an influence of a change in the potential of a substrate of the memory apparatus.

Abstract: A master slice type LSI is constructed as a three port memory circuit in which respective cells exclusively utilized as memory circuits constituting respective memory regions can be accessed simultaneously. More particularly each cell exclusively used as a memory circuit is constituted by a flip-flop circuit including two inverters (31, 32) which are connected in parallel opposition, a single write data input line (39) and two read out data output lines (40, 41) which are connected to the flip-flop circuit through transfer gate circuits (33,34,35), respectively, and at least three word lines (36, 37, 38) along which independent word signals are transmitted. The three transfer gate circuits (33, 34, 35) are independently enabled and disenabled based on the word signals transmitted over the word lines (36, 37, 38).

Abstract: To reduce the power dissipation of a static random access memory, a write enable signal is applied to the gates of load MOS transistors on bit lines which are connected to a memory cell. During the write-in time, the load MOS transistors are turned off so as to prevent as electric current from flowing from a power source into the earth through the memory cell.

Abstract: This invention relates to a semiconductor memory having flip-flops which hold the address input in order to absorb skew thereof within the same chip. The flip-flops are connected to be of the master-slave type and an address decoder is provided between the master flip-flops and the slave flip-flops. A part of the time required for latching the address signal into the master flip-flops and a part of the time required for decoder operation are overlapped, and thereby a high operation rate can be realized. Parts of the circuits forming the flip-flop circuits are used in common to the address input buffer and also in common to the word line driver circuits.

Abstract: A block oriented solid state optical memory having a distributed data storage architecture comprises a lens array including a plurality of laterally separated lenslets which have numerical apertures selected to cause them to focus essentially diffraction limited images of a photoemitter array in parallel onto laterally displaced sections of a data mask, so that the images optically align with respective photosensors. The lenslets are formed on the first surface of the lens array, and the data mask is supported on or very close to the last surface of the lens array to minimize the scattering of reflected light. An opaque light shield on the first surface of the lens array optically masks the area between the lenslets to eliminate unwanted stray light. Furthermore, in at least some embodiments of the invention, the light shield extends into the apertures of the lenslets to stop them down sufficiently to obtain substantially diffraction limited performance.

Abstract: A directory memory system including a plurality of reconfigurable subarrays of memory cells and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays. Output data from the subarrays is connected to compare data logic for comparing the subarray data to one or more bytes of compare input data, and to bit select logic for selectively placing the subarray data onto an output bus. Bypass select logic causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays, and one byte of compare input data can be bypassed to the data output port during the compare operation.

Abstract: In a magnetic bubble memory unit comprising two pairs of windings confronting in parallel each other, a printed circuit board having a magnetic bubble memory chip thereon surrounded by the windings for providing the rotating magnetic field, and a conductive shield case for covering the magnetic bubble memory chip on the printed circuit board, slitlike openings are provided on the side face of the conductive shield case so as to present connection between the printed circuit board and an external device.