Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the third semiconductor layer. The first semiconductor layer includes a first nitride semiconductor. The second semiconductor includes a second nitride semiconductor. The third semiconductor layer includes a third nitride semiconductor. The concentration of oxygen included in the second semiconductor layer is less than 5.0×1018 cm?3. The concentration of oxygen included in the third semiconductor layer is greater than or equal to 5.0×1018 cm?3.

Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.

Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.

Abstract: Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: A magnetic topological nanowire structure comprises a superconductor and a quasi-1D magnetic nanowire. The quasi-1D magnetic nanowire is coupled to or embedded in the superconductor to produce a self-contained interaction resulting in a spatially separated pair of Majorana fermions. The pair of Majorana fermions corresponds to the topological superconductor and each of the pair of the Majorana fermions are localized near a respective endpoint of the nanowire.

Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

Abstract: The present disclosure provides a graphene-based touch sensor device using triboelectric effect, the device comprising: a substrate; a first electrode layer disposed on the substrate; a graphene channel layer disposed on the substrate, wherein the graphene channel layer is flush with the first electrode layer, and is spaced from the first electrode layer; a gate dielectric layer in partial contact with the electrode layer and the graphene channel layer respectively; source and drain electrodes formed on both opposing ends of the graphene channel layer respectively; and a triboelectric layer formed on the first electrode layer, wherein the triboelectric layer generates a triboelectric potential via contact of an external friction material therewith, wherein the contact of the external friction material is detected based on a current change in the graphene channel layer due to the triboelectric potential applied thereto.

Abstract: A first conductive pattern includes: a first feeding point for supplying a potential to the first conductive pattern located at one end thereof; one or more diode elements located over the first conductive pattern; and a plurality of switching elements over the first conductive pattern on the opposite side to the first feeding point with the diode elements in between. A second conductive pattern includes a second feeding point that is provided in proximity to the first feeding point and supplies a potential different from that for the first conductive pattern to the second conductive pattern. The plurality of the switching elements is electrically connected with the second conductive pattern through a plurality of bonding wires. The second conductive pattern is provided with a slit pattern that defines an area of connection of the plurality of the bonding wires with the second conductive pattern over the second conductive pattern.

Abstract: A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.

Abstract: A component is produced by creating a first layer composite that includes a first electrically conductive substrate and having a trench filled with an insulating material by creating a second layer composite that includes the first layer composite and a structure layer. The structure layer includes an active structure and is electrically conductive at least in a first region that adjoins a first surface of the first substrate and includes in the first region of the first substrate a first electrically conductive contact face on a second surface of the first substrate, which is located opposite the first surface. The first region of the first substrate is electrically insulated laterally from other regions of the first substrate by the trench.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a sacrificial microchannel material on a device, forming an overmold material on the sacrificial microchannel material, and vaporizing the sacrificial microchannel material to form microchannel structures in the overmold that are conformal to the surfaces of the device.

Abstract: A semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of silicon and silicon oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.

Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

Abstract: A method for filling a through hole (TH) located on a substrate is provided. The TH is a continuous channel having an upper rim, a lower rim and an interior surface. In one embodiment, the method comprises steps (a)-(d). In the step (a), a conductive material (CM) is deposited over the substrate to thereby deposit a layer of the CM around the rims and on the interior surface. In the step (b), the deposited CM is etched. In particular, the etching step selectively removes more CM deposited at the rims relative to CM deposited at a mid-section of the interior surface of the channel. In the step (c), the steps (a) and (b) are optionally repeated until the channel is sealed at the mid-section by a bridge formed of CM. In the step (d), the CM is further deposited over the substrate to thereby completely fill the TH.

Abstract: The present invention provides a method for forming an organic film, including: forming a coating film by spin coating of an organic film-forming composition onto a substrate having an uneven pattern, and thereafter subjecting the substrate to a vibration treatment, and after or simultaneously with the vibration treatment, insolubilizing the coating film to an organic solvent to form the organic film. This provides a method for forming an organic film that can fill an uneven pattern on a substrate to highly flatten a substrate at low cost in a production step of a semiconductor apparatus, etc.

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Abstract: The present disclosure relates to an array substrate and manufacturing method for the same, and a display device. The array substrate comprises a plurality of pixel regions, a plurality of gate lines, and a plurality of data lines. The gate line and the data line are respectively connected to corresponding pixel regions. The pixel region comprises a common electrode and a pixel electrode arranged correspondingly. The array substrate also comprises a plurality of shield electrodes. The shield electrode is arranged to shield an electric field generated by a current flowing through the corresponding gate line. The shield electrode and the common electrode are arranged on the same layer and are insulated from each other. Since the shield electrode and the common electrode are insulated from each other, a change in the electrical signal in the shield electrode does not affect the common electrode.

Abstract: A substrate for semiconductor device includes a substrate, a reaction layer provided on a back surface of the substrate, a transmission preventing metal having a transmittance with respect to red light or infrared light lower than that of the substrate and a material of the substrate being mixed in the reaction layer, and a metal thin film layer formed on a back surface of the reaction layer and formed of the same material as the transmission preventing metal.