Abstract: A display device a display region arranged with a plurality of pixels in a matrix shape, wherein each of the plurality of pixels includes a first electrode including a first conducting layer on the first conducting layer and comprised from Mo or a Mo alloy, a second conducting layer comprised from Ag or an Ag alloy, and a third conducting layer on the second conducting layer and comprised from a metal oxide having conducting properties, the first electrode being arranged corresponding to each of the pixels respectively, a light emitting layer above the third conducting layer and emitting light according to a current supply, and a second electrode above the light emitting layer and allowing at least a part of the light from the light emitting layer to pass through.

Abstract: A disclosed photosensor includes: a first electrode layer including a reflection part having an inclination surface; a first semiconductor layer positioned on the first electrode layer; a second electrode layer positioned on the first semiconductor layer; and a first dielectric layer and a second dielectric layer sequentially positioned on the second electrode layer, wherein the first dielectric layer and the second dielectric layer have different dielectric constant values. Further, the disclosed display device includes a plurality of pixel areas positioned on a substrate, and a sensor unit formed in at least some pixel areas among the plurality of pixel areas.

Abstract: A voltage equal to the threshold value of a TFT (106) is held in capacitor unit (109). When a video signal is inputted from a source signal line, the voltage held in the capacitor unit is added thereto and a resultant signal is applied to a gate electrode of the TFT (106). Even when a threshold value is varied for each pixel, each threshold value is held in the capacitor unit (109) for each pixel. Thus, the influence of a variation in threshold value can be eliminated. Further, holding of the threshold value is conducted by only the capacitor unit (109) and a charge does not move at writing of a video signal so that a voltage between both electrodes is not changed. Thus, it is not influenced by a variation in capacitance value.

Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.

Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.

Abstract: Provided is an LED package which is unlikely to cause the attenuation of emitted light from an LED element by bonding wires for electrical connection of the LED element. The LED package includes a board including a pair of connection electrodes formed thereon, an LED element mounted on the board, a bonding wire electrically connecting the LED element to the pair of connection electrodes, and a covering layer containing a phosphor and covering the bonding wire, wherein the phosphor is excited by emitted light from the LED element to emit light having an absorbance in the bonding wire lower than that of the emitted light and a wavelength longer than that of the emitted light.

Abstract: A silicon carbide substrate includes a Si substrate (silicon substrate), a SiC base film (silicon carbide base film) which is stacked on the Si substrate and contains silicon carbide, a defective part (through-hole) which passes through the SiC base film, a hole which is located between the Si substrate and the SiC base film corresponding to the defective part, and an oxide film which is provided on the surface of the Si substrate in the hole and contains silicon oxide. Further, on the SiC base film, a SiC grown layer (silicon carbide grown layer) may be formed.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: A carrier tape comprises a flexible body portion having a top surface. The flexible body portion comprises a plurality of pockets. Each of the plurality of pockets comprises pocket side walls, a base bottom portion fully circulating a raised bottom portion of a pedestal. The pedestal is made up of the raised bottom portion and pedestal side walls. The pedestal sidewalls, the base bottom portion and a lower part of the pocket side walls constitute a trench fully circulating the pedestal.

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: The present invention discloses an InGaAs film grown on a Si substrate, which comprises a Si substrate, a low temperature In0.4Ga0.6As buffer layer, a high temperature In0.4Ga0.6As buffer layer and an In0.53Ga0.47As epitaxial film, arranged sequentially, wherein the low temperature In0.4Ga0.6As buffer layer is an In0.4Ga0.6As buffer layer grown at the temperature of 350˜380° C.; the high temperature In0.4Ga0.6As buffer layer is an In0.4Ga0.6As buffer layer grown at the temperature of 500˜540° C., and the sum of the thickness of the low temperature In0.4Ga0.6As buffer layer and the thickness of the high temperature In0.4Ga0.6As buffer layer is 10˜20 nm. The invention further discloses a method for preparing the InGaAs film. The InGaAs film grown on the Si substrate of the present invention has good crystal quality, is almost completely relaxed, and has a simple preparation process.

Abstract: A spatial terahertz wave phase modulator based on the high electron mobility transistor is provided. The phase modulator combines the quick-response high electron mobility transistor with a novel metamaterial resonant structure, so as to rapidly modulate terahertz wave phases in a free space. The phase modulator includes a semiconductor substrate, an HEMT epitaxial layer, a periodical metamaterial resonant structure and a muff-coupling circuit. A concentration of 2-dimensional electron gas in the HEMT epitaxial layer is controlled through loading voltage signals, so as to change an electromagnetic resonation mode of the metamaterial resonant structure, thereby achieving phase modulation of terahertz waves. The phase modulator has a phase modulation depth of over 90 degrees within a large bandwidth, and a maximum phase modulation depth is about 140 degrees. Furthermore, the phase modulator is simple in structure, easy to machine, high in modulation speed, convenient to use, and easy to package.

Abstract: A method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers includes forming an electrically conductive layer on a surface of a first semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the first semiconductor wafer and the first semiconductor wafer. The method further includes forming an electrically conductive layer on a surface of a second semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the second semiconductor wafer and the second semiconductor wafer. A material composition of the electrically conductive layers formed on the first and second semiconductor wafers are selected based on a value of the physical property of the first and second semiconductor wafers, respectively. The material composition of the electrically conductive layers formed on the first and second semiconductor wafers are different.

Abstract: The invention provides a metal oxide semiconductor layer forming composition containing a solvent represented by formula [1]: (wherein R1 represents a C2 to C3 linear or branched alkylene group, and R2 represents a C1 to C3 linear or branched alkyl group) and an inorganic metal salt.

Abstract: An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad.

Abstract: Embodiments disclosed herein generally relate to a multilayer magnetic device, and specifically to a spin-torque transfer magnetoresistive random access memory (STT-MRAM) device which provides for a reduction in the amount of current required for switching individual bits. As such, a polarizing reference layer consisting of a synthetic antiferromagnet (SAF) structure with an in-plane magnetized ferromagnet film indirectly exchange coupled to a magnetic film with perpendicular magnetic anisotropy (PMA) is disclosed. By tuning the exchange coupling strength and the PMA, the layers of the SAF may both be canted such that either may be used as a tilted polarizer for either an in-plane free layer or a free layer with PMA.

Abstract: A light-emitting display device includes a substrate, several light emitting units for emitting light with different wavelengths, and an optical lens. The substrate has at least one receiver for containing these light emitting units. A light guide structure of the light-emitting display device can be the receiver with a specific designed, a frame body with at least one corresponding through hole formed on the corresponding receiver, or at least one optical element formed on the corresponding receiver, so as the light emitted by the light emitting units can be reflected towards the preset optical axis. And the optical lens is formed on the light guide structure as medium for mixing lights of different wavelengths for achieving a uniform lighting effect.

Abstract: Measures are described with the aid of which not only a rupture, but also cracks may be detected in the diaphragm structure of a micromechanical component with the aid of circuit means integrated into the diaphragm structure. At least some circuit elements are integrated for this purpose into the bottom side of the diaphragm, i.e., into a diaphragm area directly adjoining the cavern below the diaphragm.

Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.