Abstract: A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.

Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.

Abstract: A light-emitting device includes a substrate having a first surface extended in a first direction, a second surface opposite to the first surface, a third surface between the first and second surfaces and extended in the first direction, and a fourth surface opposite to the third surface, a conductive member including at least four element mounting portions arranged in the first direction on the first surface, a first wiring portion on the second surface, a second wiring portion on the third surface, and a third wiring portion on the fourth surface, and first, second, third, and fourth light-emitting elements respectively mounted on the four element mounting portions. With the first, second, and third wiring portions, the first and second light-emitting elements are connected in series, the third and fourth light-emitting elements are connected in series, and the first and third light-emitting elements are connected in parallel.

Abstract: A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations.

Abstract: The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer S1, a second oxide semiconductor layer S2, and a third oxide semiconductor layer S3 are sequentially stacked, so that the oxide semiconductor layer through which carriers flow is separated from the gate insulating film containing silicon. The thickness of the first oxide semiconductor layer S1 is preferably smaller than those of the second oxide semiconductor layer S2 and the third oxide semiconductor layer S3, and is less than or equal to 10 nm, preferably less than or equal to 5 nm.

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

Abstract: A composite quantum-dot photodetector comprising a substrate with a colloidally deposited thin film structure forming a photosensitive region, the thin film containing at least one type of a nanocrystal quantum-dot, whereby the nanocrystal quantum dots are spaced by ligands to form a lattice, and the lattice of the quantum dots has an infill material that forms an inorganic matrix that isolates the nanocrystal quantum dots from atmospheric exposure.

Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.

Abstract: A manufacturing method of a solid state imaging device according to one embodiment includes the steps of forming, on a substrate, a gate electrode of a first transistor and a gate electrode of a second transistor adjacent to the first transistor; forming an insulator film covering the gate electrode of the first transistor and the gate electrode of the second transistor such that a void is formed between the gate electrode of the first transistor and the gate electrode of the second transistor; forming a film on the insulator film; and forming a light shielding member by removing a part of the film by an etching.

Abstract: A system and method of reducing spin pumping induced damping of a free layer of a memory device is disclosed. The memory device includes an anti-ferromagnetic material (AFM) pinning layer in contact with a bit line access electrode. The memory device also includes a pinned layer in contact with the AFM pinning layer, a tunnel barrier layer in contact with the pinned layer, and a free layer in contact with the tunnel barrier layer. The memory device includes a spin torque enhancing layer in contact with the free layer and in contact with an access transistor electrode. The spin torque enhancing layer is configured to substantially reduce spin pumping induced damping of the free layer.

Abstract: Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Abstract: A light emitting device is constituted with a semiconductor light emitting element on which a support member is disposed on one surface provided with a p-side electrode and an n-side electrode and a fluorescent material layer is disposed on the other surface which is an opposite side of the one surface. The support member includes a resin layer, an electrode for p-side external connection and an electrode for n-side external connection disposed exposed at a surface opposite side of a surface where the resin layer is in touch with a light emitting element, and internal wirings disposed in the resin layer and electrically connecting between a p-side electrode and the electrode for p-side external connection respectively. The internal wirings include a metal wire and a metal plated layer, and a metal wire and a metal plated layer respectively connected in series.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and intermediate mold layers on a substrate, forming first upper mold patterns and first spacers on the first and second regions, respectively, of the substrate, etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively, forming second spacers to cover sidewalls of the first and second intermediate mold patterns, etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns, and etching the substrate using the lower mold patterns as an etch mask to form active patterns.

Abstract: Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes: a substrate; a plurality of pixel units provided on the substrate, each of the pixel units including a plurality of functional layers; and a light shielding assembly arranged between adjacent pixel units. The light shielding assembly including: a light shielding layer; a light absorption layer overlaid on the light shielding layer; and an antireflection layer overlaid on the light absorption layer. By means of providing an antireflection layer the light shielding assembly, it can decrease the reflection of the external ambient light on the light shielding assembly, thereby improving the display contrast and the image display quality.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.