Patents Examined by Jami Valentine Miller
  • Patent number: 11228087
    Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes an antenna circuit chip, a first packaging layer, a first rewiring layer, an antenna structure, a second metal connecting column, a third packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using the rewiring layer and the metal connecting column.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 18, 2022
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 11227793
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Nicole Saulnier
  • Patent number: 11222921
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Patent number: 11222920
    Abstract: A magnetic device includes a first electrode, a second electrode, a plurality of magnetic junctions each containing a ferromagnetic reference layer and a ferromagnetic free layer located between the first electrode and the second electrode, and a plurality of magnetoelectric multiferroic portions having different structural defect densities located between the first electrode and the second electrode. Each of the plurality of magnetoelectric multiferroic portions is magnetically coupled to the ferromagnetic free layer of a respective one of the plurality of magnetic junctions.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: January 11, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Alan Kalitsov
  • Patent number: 11217492
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 11217731
    Abstract: An adhesive layer is disclosed and may include a plurality of short chain molecules, each of the plurality of the short chain molecules including a first end and a second end such that the distance between the first end and second end is less than 100 nm and such that first end is configured to attach to a first surface and the second end is configured to attach to a second surface.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 4, 2022
    Assignee: Lumileds LLC
    Inventors: Venkata Ananth Tamma, Kentaro Shimizu, Vernon K. Wong
  • Patent number: 11217744
    Abstract: A magnetic memory device includes an MTJ element between a bottom electrode layer and a top electrode layer. The MTJ element comprises a reference layer, a tunnel barrier layer and a free layer. The reference layer comprises sub-layers that protrude beyond a sidewall of the tunnel barrier layer. The tunnel barrier layer protrudes beyond a sidewall of one of sub-layers of the free layer. Sidewall spacers are disposed to respectively cover a sidewall of the top electrode layer, sidewalls of the sub-layers of the free layer, a sidewall of the tunnel barrier layer, and sidewalls of the sub-layers of the reference layer. The etching of the MTJ stack and the formation of the sidewall spacers are carried out in the same HDPCVD chamber without breaking the vacuum.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 4, 2022
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11217746
    Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 11211552
    Abstract: This spin-orbit torque magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; a non-magnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer; and a spin-orbit torque wiring on which the first ferromagnetic layer is laminated, wherein the spin-orbit torque wiring extends in a second direction crossing a first direction which is an orthogonal direction of the first ferromagnetic layer, the first ferromagnetic layer includes a first laminate structure and an interfacial magnetic layer in order from the spin-orbit torque wiring side, the first laminate structure is a structure obtained by arranging a ferromagnetic conductor layer and an oxide-containing layer in order from the spin-orbit torque wiring side, the ferromagnetic conductor layer includes a ferromagnetic metal element, and the oxide-containing layer includes an oxide of a ferromagnetic metal element.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 28, 2021
    Assignee: TDK CORPORATION
    Inventor: Yohei Shiokawa
  • Patent number: 11211259
    Abstract: A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu-Fang Chen, Shi-Chieh Lin, Victor Y. Lu, Yeur-Luen Tu
  • Patent number: 11211498
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 11205679
    Abstract: A magnetic memory device includes a conductive line extending in a first direction, a bottom electrode provided on a portion of a bottom surface of the conductive line, a free layer and a pinned layer stacked on the conductive line, a spacer layer between the free layer and the pinned layer, and a top electrode provided on a portion of a top surface of the pinned layer. The conductive line, the free layer, the pinned layer and the spacer layer have side surfaces perpendicular to the first direction, and the side surfaces are aligned with each other.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 21, 2021
    Inventors: Sung Chul Lee, Eunsun Noh, Jeong-Heon Park, Ung Hwan Pi
  • Patent number: 11205678
    Abstract: Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Ekmini Anuja De Silva, Dominik Metzler
  • Patent number: 11195843
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: December 7, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroki Yamashita
  • Patent number: 11189540
    Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
  • Patent number: 11183634
    Abstract: A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Woo Tae Lee, Beom Seok Lee
  • Patent number: 11167983
    Abstract: A method includes attaching an optically transparent wafer to a first surface of an interposer wafer. The interposer wafer has a second surface opposite the first surface, and the second surface has a first channel therein. The method further includes attaching the interposer wafer to a first surface of a semiconductor wafer, and etching a second channel through the optically transparent wafer and through the interposer wafer. The method then includes applying wax into the second channel, and sawing through the optically transparent wafer and through at least a portion of the interposer wafer to form a third channel having a width that is wider than a width of the second channel. The wax is then removed to expose a portion of the first surface of the semiconductor wafer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: John Charles Ehmke
  • Patent number: 11169227
    Abstract: The present disclosure generally relates to a Wheatstone bridge that includes a plurality of resistors comprising dual free layer (DFL) TMR structures. The DFL TMR structures include one or more hard bias structures on the side of DLF. Additionally, one or more soft bias structures may also be present on a side of the DFL. Two resistors will have identical hard bias material while two other resistors will have hard bias material that is identical to each other, yet different when compared to the first two resistors. The hard bias materials will provide opposite magnetizations that will provide opposite bias fields that result in two different magnetoresistance responses for the DFL TMR.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chih-Ching Hu, Yung-Hung Wang, Yuankai Zheng, Chen-jung Chien, Ming Mao, Daniele Mauri, Ming Jiang
  • Patent number: 11171285
    Abstract: Provided is a non-ferromagnetic spacing composite layer, comprising first, second and third spacing layers stacked in sequence. The first and third spacing layers are each made of Re, Rh, Ir, W, Mo, Ta, or Nb, and the second spacing layer is made of Ru. The second spacing layer has a thickness of equal to or more than 0.18 nm, and the non-ferromagnetic spacing composite layer has a total thickness of 0.6 nm to 1 nm. Also, provided are a method of preparing the non-ferromagnetic spacing composite layer, a synthetic antiferromagnetic laminated structure, and an MRAM. The synthetic antiferromagnetic laminated structure can maintain a certain coupling strength and the RKKY indirect interaction after thermal treatment, thereby keeping the recording function of MRAM.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 9, 2021
    Assignee: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chih-Huang Lai, Chun-Liang Yang, Yi-Huan Chung, Wei-Chih Huang, Chih-Wen Tang, Hui-Wen Cheng
  • Patent number: 11171178
    Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers comprises a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the insulating layer and between the conductive lines to expose, in sidewalls of the hole, conductive lines of the first to Nth layers; a variable resistance layer disposed on sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed, wherein N is a natural number of two or more.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 9, 2021
    Assignee: SK HYNIX INC.
    Inventors: Jae-Hyun Han, Hyang-Keun Yoo, Se-Ho Lee