Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: An image sensor includes: a substrate having a first surface and a second surface that are opposite to each other; a plurality of color filters on the substrate; a fence pattern between adjacent color filters of the plurality of color filters; and a protective layer between the substrate and the plurality of color filters, wherein the protective layer covers the fence pattern. The fence pattern includes: a first fence pattern having a first bottom surface and a first top surface that are opposite to each other; and a second fence pattern on the first top surface of the first fence pattern. A width at the first bottom surface of the first fence pattern is less than a width of the second fence pattern, and the protective layer covers a sidewall of the first fence pattern.

Abstract: The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

Abstract: A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.

Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.

Abstract: A magnetic memory device includes a substrate; a first magnetoresistive effect element; and a second magnetoresistive effect element provided at a side of the first magnetoresistive effect element opposite to a side of the first magnetoresistive effect element at which the substrate is provided. A heat absorption rate of the first magnetoresistive effect element is lower than a heat absorption rate of the second magnetoresistive effect element.

Abstract: The material layer stack includes first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion. A tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque. Magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.

Abstract: A spin-orbit-torque magnetization rotational element includes: a ferromagnetic metal layer, a magnetization direction of the ferromagnetic metal layer being configured to change; a spin-orbit torque wiring which extends in the first direction intersecting a lamination direction of the ferromagnetic metal layer and is joined to the ferromagnetic metal layer; and two via wires, each of which extends in a direction intersecting the spin-orbit torque wiring from a surface of the spin-orbit torque wiring opposite to a side with the ferromagnetic metal layer and is connected to a semiconductor circuit, wherein a via-to-via distance between the two via wires in the first direction is shorter than a width of the ferromagnetic metal layer in the first direction.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

Abstract: A device including a templating structure and a magnetic layer on the templating structure is described. The templating structure includes D and E. A ratio of D to E is represented by D1-xEx, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. Further, E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir, D includes at least 50 atomic percent of the at least one constituent. The templating structure is nonmagnetic at room temperature. The magnetic layer includes at least one of a Heusler compound and an L10 compound, the magnetic layer being in contact with the templating structure.

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

Abstract: A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.