Abstract: A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.

Abstract: A magnetization rotational element includes a spin-orbit torque wiring, and a first ferromagnetic layer which is located in a first direction with respect to the spin-orbit torque wiring and in which spins are injected from the spin-orbit torque wiring. The spin-orbit torque wiring has a plurality of spin generation layers and insertion layers located between the plurality of spin generation layers in the first direction. The insertion layers have a lower electrical resistivity than the spin generation layers.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: A memory device includes a substrate, a laminated structure and a memory string. The laminated structure is disposed on the substrate. The laminated structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The memory string is accommodated in the laminated structure along the first direction. The memory string includes a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer. At least a portion of the memory layer and the insulating layers are overlapped along the first direction.

Abstract: A device including a templating structure and a magnetic layer is described. The templating structure includes D and E. A ratio of D to E is represented by D1-xEx, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir. D includes at least 50 atomic percent of the at least one constituent. The magnetic layer is on the templating structure and includes at least one of a Heusler compound and an L10 compound. The magnetic layer is in contact with the templating structure and being magnetic at room temperature.

Abstract: A spin element according to the present embodiment includes a wiring, a laminate including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part with the first ferromagnetic layer therebetween in a plan view in a lamination direction, and an intermediate layer which is in contact with the wiring and is between the first conductive part and the wiring, wherein a diffusion coefficient of a second element including the intermediate layer with respect to a first element including the wiring is smaller than a diffusion coefficient of a third element constituting the first conductive part with respect to the first element or a diffusion coefficient of the third element including the first conductive part with respect to the second element constituting the wiring is smaller than a diffusion coefficient of the third element with respect to the first element constituting the intermediate layer.

Abstract: Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a spin traversing along the band for a complete cycle will recover its original position, while having rotated away from its original orientation. The spins can respond to an external magnetic field, but cannot achieve a ferromagnetic state, in which all magnetic moments are pointing in the same direction, due to the topological knot. 3D assemblies of such nano-Möbius strips may form prototype secure magnetic information storage devices that are secure and with extremely low levels of energy dissipation.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.

Abstract: The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Abstract: According to one embodiment, a magnetic memory device includes: a plurality of first films and a plurality of second films stacked alternately; a first insulating layer passing through the plurality of first and second films; a second insulating layer passing through the plurality of first and second films and in contact with a surface of the first insulating layer; a first magnet including a first pillar portion provided between the second insulating layer and the plurality of first and second films, and a first terrace portion coupled to one end of the first pillar portion; a first interconnect layer coupled to the other end of the first pillar portion of the first magnet; and a first magnetoresistance effect element coupled to the first terrace portion of the first magnet.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

Abstract: In one embodiment, the magnetic memory device includes a free layer structure having a variable magnetization direction. The free layer structure includes a first free layer, the first free layer being a first Heusler alloy; a coupling layer on the first free layer, the coupling layer including a metal oxide layer; and a second free layer on the metal oxide layer, the second free layer being a second Heusler alloy, the second Heusler alloy being different from the first Heusler alloy.

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes an antenna circuit chip, a first packaging layer, a first rewiring layer, an antenna structure, a second metal connecting column, a third packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using the rewiring layer and the metal connecting column.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.