Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: A method of manufacturing a crystalline silicon film excellent in crystallinity. When using elements such as nickel as metal elements that promotes the crystallization of the amorphous silicon film, nickel is allowed to be contained in a solution repelled by the surface of the amorphous silicon film. Then, a part of the amorphous silicon film is removed, and the solution is held in only that part. In this way, the nickel elements are selectively introduced into a part of the amorphous silicon film, and a heat treatment is also conducted to allow crystal growth to proceed from that portion toward a direction parallel to a substrate.

Abstract: The present invention refers to a method of producing a ferroelectric memory which method comprises: a) providing ferroelectric particles, b) providing a substrate, c) orientating at least a subset of said ferroelectric particles such that there is an axis of said particles along which axis a dipole moment may be directed in the ferroelectric state, said axis having an orientation the average of which is in at least one predetermined direction with regard to a surface of said substrate, d) allowing said ferroelectric particles to attach to said substrate, and to a method of storing information on a substrate, and to a memory device.

Abstract: A non-volatile memory IGFET device has a gate dielectric stack that is di lectrically equivalent to a layer of silicon dioxide having a thickness of to 170 Å or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 1011/cm3, or less, without significantly compromising the program speed.

Abstract: A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

Abstract: There is provided a method for forming a vertical gate on a vertical array semiconductor device having support devices. The method includes the step of forming a pedestal of the vertical gate from SiGe. The pedestal is etched in a gate conductor (GC) post etch treatment (PET) that is selective with respect to the support devices. A trench top nitride spacer process is performed to obtain a GC SiN spacer combined with a DT (deep trench) top SiN spacer, wherein the GC SiN spacer and the DT top SiN spacer isolate a bitline contact from the vertical gate with respect to critical dimension and overlay.

Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.

Abstract: Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

Abstract: For suppressing decomposition of an organic group (for example, a CH3 group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

Abstract: In the method of producing the 3-5 group compound semiconductor carrying out the lateral direction selective growth of the desired GaN type 3-5 group compound-semiconductor layer on this c-plane by the stripe mask formed on the c-plane of the underlying crystal containing a GaN type 3-5 group compound semiconductor, a stripe mask is formed on the underlying crystal such that the direction of the stripe is rotated 0.095° or more and less than 9.6° from <1-100> direction, and with using this stripe mask, the lateral direction selective growth of the GaN type 3-5 group compound-semiconductor layer is carried out, and a high quality 3-5 group compound-semiconductor layer can be formed on the underlying crystal.

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.

Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.

Abstract: The present invention is generally directed to a method of reducing oxidation of metal structures using ion implantation, and a device constructed in accordance with the method. In one illustrative embodiment, the method comprises providing a semiconducting substrate having a first layer of insulating material formed thereabove, the first layer of insulating material having at least one conductive structure positioned therein, and performing an ion implant process to implant ions into at least the one conductive structure.

Abstract: A conductive composition of titanium boronitride (TiBxNy) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the titanium boronitride is used to construct contact pads such as inline pads, backend pads, sensors or probes. Advantages of embodiments of the titanium boronitride include reduced scratching, increased hardness, finer granularity, thermal stability, good adhesion, and low bulk resistivity. Exemplary methods of creating the titanium boronitride include a sputtering process and a plasma anneal process.

Abstract: A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a sacrificial layer of silicon nitride; using a masks for defining line structures in the layer of silicon nitride for the bit line implant processes; depositing a dielectric material among the line structures to fill gaps among the line structures; planarizing the deposited oxide and said layer of silicon nitride; removing the silicon nitride and applying a layer of polysilicon material; patterning wordlines in the array portion, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.

Abstract: Many integrated circuits, particularly digital memories, include millions of field-effect transistors which operate simultaneously and thus consume considerable power. One way to reduce power consumption is to lower transistor threshold, or turn-on, voltage, and then use lower-voltage power supplies. Although conventional techniques of lowering threshold voltage have enabled use of 2-volt power supplies, even lower voltages are needed. Several proposals involving a dynamic threshold concept have been promising, but have failed, primarily because of circuit-space considerations, to yield practical devices. Accordingly, the present invention provides a space-saving structure for a field-effect transistor having a dynamic threshold voltage. One embodiment includes a vertical gate-to-body coupling capacitor that reduces the surface area required to realize the dynamic threshold concept. Other embodiments include an inverter, voltage sense amplifier, and a memory.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

Abstract: A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (102). First and second gate dielectrics (120, 142) are formed on the channel structure's first and second major surfaces respectively. First and second gate dielectrics (120, 142) differ in at least one characteristic. First and second gate electrodes (116, 152) are formed in contact with the first and second gate dielectrics (120, 142) respectively. The first and second gate electrodes (116, 152) differ in at least one characteristic. First and second gate dielectrics (120, 142) may have different dielectric constants while first and second gate electrodes (116, 152) may have different doping and conducting properties.