Abstract: A method of forming a plurality of individual semiconductor chip modules wherein a plurality of chips are placed in a plurality of chip compartments formed by adhering a support panel to the first surface and a cover panel to the second surface of a stiffener panel having openings defining sidewalls of the chip compartments. The resulting laminated panel structure is then cut into a plurality of modules each having at least one compartment containing at least one chip. Each chip is electrically connected to interior conductive pads on the inner surface of the support panel, and these interior pads in turn are connected by conductive paths to exterior conductive terminals deposited on the outer surface of the support panel. The electrical connections between the chip and the interior conductive pads of the support panel may be encapsulated in a polymeric material before the cover panel is adhered to the stiffener panel.

Abstract: The present invention is directed to an automated method of controlling photoresist develop time to control critical dimensions, and a system for accomplishing same. In one embodiment, the method comprises measuring a critical dimension of each of a plurality of features formed in a layer of photoresist, providing the measured critical dimensions of the features, in the layer of photoresist to a controller that determines, based upon the measured critical dimensions, a duration of a photoresist develop process to be performed on a layer of photoresist formed above a subsequently processed wafer, and performing a photoresist develop process on the subsequently processed wafer for the determined duration.

Abstract: A method for controlling stoichiometry of dielectric films, e.g., BST films, preferably formed at low deposition temperatures. A deposition process may use an adjustment in oxidizer flow and/or partial pressure, the provision of a hydrogen-containing component, an adjustment in hydrogen-containing component flow and/or partial pressure, an adjustment in deposition pressure, and/or a modification of system component parameters (e.g., heating a shower head or adjusting a distance between a shower head of the deposition system and a wafer upon which the film is to be deposited), to control the characteristics of the dielectric film, e.g., film stoichiometry.

Abstract: An object of the present invention is to provide a film-forming method, a film-forming system, etc. capable of achieving adequate thickness repeatability and uniformity and sufficiently large film-forming rates in film formation of a thin film on a substrate to be treated and also capable of simplifying a system configuration. A thermal treatment system 1 according to the present invention is a system for forming a thin film of SiO2 on an Si wafer W and is provided with a reactant gas exhaust system 15 for reducing the pressure around the Si wafer W, a reactant gas supply system 14 for supplying hydrogen gas Gh and oxygen gas Go so as to mix them, onto the Si wafer W, and a chamber 2 having a lamp group 9G for heating the Si wafer W, and a wafer support member 3.

Abstract: A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack.

Abstract: A method for fabricating a semiconductor device employing a salicide (self-aligned silicide) structure is disclosed. The method prevents a junction leakage current from being increased at a portion of a source/drain region which is adjacent to an field oxide, by forming the source/drain region comprised of a relatively deep SID region and a relatively shallow SID region, wherein the deep SID region is formed adjacent to the field oxide and the shallow SID region is formed adjacent to the insulating film spacer.

Abstract: A method and apparatus for fabricating a metamorphic long-wavelength, high-speed photodiode, wherein a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading region which grades past the desired lattice constant is configured at a low temperature. A reverse grade back is performed to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in a grading layer and a reverse grading layer. Thereon a strained layer superlattice substrate is created upon which a high-speed photodiode can be formed. Implant or diffusion layers grown in dopants can be formed based on materials, such as Be, Mg, C, Te, Si, Se, Zn, or others. A metal layer can be formed over a cap above a P+ region situated directly over an N-active region. The active region also includes a p-doped region.

Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A plurality of active pixel sensors are formed on the surface of a semiconductor wafer. The semiconductor wafer comprises a P-type substrate, an active pixel sensor region and a periphery circuit region. A first active pixel sensor block mask (APSB mask) is formed to cover the active pixel sensor region, then at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask is formed. A second APSB mask and at least one N-well mask are formed to cover the active pixel sensor region and the region outside the P-well region. At least one P-well on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask is formed. Finally, at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.

Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.

Abstract: Electrical connection of a measuring socket to an IC package, to measure electrical characteristics of the IC package, is realized by bringing a measuring pin of a measuring arm of the measuring socket into contact with an end surface of a distal end of a lead of the IC package. Accordingly, a problem of solder plated to the lead becoming attached to and deposited on an upper side of a socket pin and shaved off by the distal end of the lead, and thereby producing solder residue, is solved. This problem occurs when electrical connection to an IC package is conventionally realized by bringing the distal end of the lead of the IC package into contact with a distal end of the socket pin.

Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.

Abstract: Embodiments in accordance with the present invention provide methods of forming such dielectric materials, dielectric material layers and various semiconductor devices that employ such materials and layers. In general, embodiments of the present invention provide for physically vapor forming a high purity metal layer over the semiconductor substrate and after forming such a layer oxidizing the high purity metal layer to form the dielectric material employing atomic oxygen generated in a high density plasma environment. Such a dielectric material is useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like.

Abstract: A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.

Abstract: A method for depositing an undoped silicate glass layer. An undoped silicon glass layer is formed to fill a recessed region in a semiconductor substrate by performing at least three chemical vapor depositions. The recessed region is a trench of a shallow trench isolation, or a gap between a plurality of polysilicon or conductive layers. At each pass, under deposition conditions that are as conventionally defined, this method comprises increasing the number of times of deposition performed on the substrate and decreasing the time of each deposition inside a reaction chamber in order to have the thickness of the undoped silicate glass thinner. In this manner, the gap filling ability is enhanced and void formation is prevented. This method also includes, before each deposition is performed, rotating the semiconductor substrate a given angle in a clockwise or counter-clockwise direction so that by the last deposition, the semiconductor substrate has rotated a total of 360° or a multiple of 360°.

Abstract: A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

Abstract: Efficient methods are disclosed for fabricating metal plated spring structures in which the metal is plated onto the spring structure after release. A conductive release layer is deposited on a substrate and a spring metal layer is then formed thereon. A first mask is then used to form a spring metal finger, but etching is stopped before the release layer is entirely removed. A second mask is then deposited that defines a release window used to remove a portion of the release layer and release a free end of the spring metal finger. The second mask is also used to plate at least some portions of the free end of the finger and selected structures exposed through the second mask. Remaining portions of the release layer are utilized as electrodes during electroplating. The resulting spring structure includes plated metal on both upper and lower surfaces of the finger.