Abstract: The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: A method of manufacturing a solid-state image pickup device including the steps of preparing a package including a housing section to house a solid-state image pickup element chip and an opening section in an upper section thereof, sporadically applying adhesive with a predetermined thickness on a bottom surface of the housing section, moving the solid-state image pickup element toward the housing section, an upper surface of the package and an upper surface of the element each having desired parallelism with respect to a predetermined reference surface with high precision, bringing a rear surface of the solid-state image pickup element into contact with the adhesive and stopping the movement of the element before the element comes into contact with the bottom surface of the housing section, curing the adhesive while the solid-state image pickup element is floating on the adhesive and fixing the element in the housing section.

Abstract: A substrate support rim used in the fabrication of devices such as organic light emissive diodes (OLEDs) is disclosed. The support rim, which is located at the edge of a substrate, serves to reinforce the substrate, facilitating handling during and after the fabrication process to reduce damage to the device. The support rim comprises, for example, epoxy, adhesives or other materials that adhere to the substrate.

Abstract: A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: A stacked semiconductor package including: a first chip; a plurality of first leads of which one side of each of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including holes for exposing a predetermined portion of each of the plurality of the first leads, and the first molding compound does not cover a side of the first leads opposite the holes; a first conductive portion formed within the holes included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically co

Abstract: A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. The second dummy gates and spacers are removed. A first metal layer is deposited overlying the substrate and patterned to form a first metal gate in one of the NMOS and PMOS active areas.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. A gate electrode, insulating layer, semiconductor layer, doped silicon layer and metal layer are formed on a substrate. A first photoresist layer with a first absorptivity is formed on the metal layer. A second photoresist layer with a second absorptivity is formed on the first photoresist layer. The second absorptivity is higher than the first absorptivity. An exposure process and a development process are performed to form a first pattern on the first photoresist layer and a second pattern on the second photoresist layer at the same time. An etching process is then performed to transfer the first pattern into the semiconductor layer, the doped silicon layer and the metal layer and transfer the second pattern into the doped silicon layer and the metal layer. After performing the etching process, the first photoresist layer and the second photoresist layer are removed.

Abstract: In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active area to accommodate source/drain doping. In another preferred implementation, desired PMOS regions over a substrate into which p-type impurity is to be provided are exposed while a contact opening is contemporaneously formed to at least one conductive line extending over substrate isolation oxide. In another preferred implementation, a contact opening to a conductive line over a substrate and an opening to a laterally spaced substrate active area are formed in a common masking step. In another preferred implementation, desired PMOS active areas over a substrate are exposed and p-type impurity to a first concentration is provided into desired exposed areas.

Abstract: A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created. Under the first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited, The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched. Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Abstract: A semiconductor lamination including an n-type layer and a p-type layer composed of a gallium nitride based compound semiconductor and forming a light emitting region is formed on the surface of a substrate. A p-side electrode is formed through a diffusion metal layer on the surface of the semiconductor lamination. Also, an n-side electrode is formed on the n-type layer exposed by etching off a part of the semiconductor lamination. The n-side electrode is formed of an ohmic contact electrode and a bonding electrode. The bonding electrode is formed in such a manner as to cover the surface and the sides of the ohmic contact electrode. As a result, a semiconductor light emitting device made of a gallium nitride based compound semiconductor is produced having an electrode structure of a superior ohmic contact characteristic and a superior wire bonding characteristic.

Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

Abstract: This invention provides a patterning method for a transparent electrode capable of preventing heat damages and insulation failure or the like even when a ZnO film is used. An ITO film 3 is formed on a transparent substrate 1 by sputtering and the ZnO film 4 is formed on the ITO film 3 by sputtering. Then, regions to be irradiated of the ITO film 3 and the ZnO film 4 are eliminated and patterned by Nd-YAG laser irradiation.

Abstract: In forming a conduction film in a semiconductor device, after an uneven natural oxide film on a silicon film has been once removed, an even and clean silicon oxide film is formed by an oxidizing chemical solution treatment. After that, a silicide film is formed, thus forming a stable conduction film consisting of a two-layered structure of a polysilicon/silicide film.

Abstract: A premold type semiconductor package includes a plurality of leads arranged side by side and having upper and lower common surfaces, a mold resin integrally molded with the leads for securing them from the upper and lower surfaces thereof. The mold resin defines a chip mounting recess at an upper side on the first surfaces of the leads, so that a semiconductor chip is to be mounted in the recess. The upper surfaces of the leads are partially exposed in the recess so as to define internal connecting terminals to which the semiconductor chip is to be electrically connected. The mold resin is provided with a plurality of holes by which the lower surfaces of the leads are partially exposed to define external connecting terminals.

Abstract: A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination zone provided at the surface of the transistor includes the steps of producing the horizontal polysilicon gate first and then introducing the recombination zone. The process allows producing a transistor without encountering problems caused by the insufficient high-temperature compatibility of metals.