Abstract: An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each of the unit pixels includes, a photoelectric element for sensing a light beam incident thereto and generating photoelectric charges, a transistor including a gate dielectric formed adjacent to the photoelectric element and a gate electrode formed on top of the gate dielectric and a capacitor structure including an insulating film formed on a portion of the photoelectric element and a bottom electrode, wherein the insulating film and the gate dielectric are made of a same material and the bottom electrode and the gate electrode are made of a same material.

Abstract: A connection component is made by providing an assembly comprising a base layer of a dielectric material, a metal layer overlying the base layer, and a top layer of a plasma-etchable material overlying the metal layer; forming openings in the top layer to produce a top layer mask; and forming first conductive elements from the metal layer by removing metal from regions of the metal layer aligned with the openings in the top layer mask. This method may be used to form a connection component having vias or bond windows formed therein for connection with other elements of a microelectronic device and conductive elements may be formed on either or both sides of the base layer.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: For suppressing decomposition of organic group (for example, CH3 group) during ashing process, which is bonded to Si atom of an organic SOG film or layer for use in flattening process, a method comprises following steps: forming an organic SOG layer directly or through a predetermined film including a hillock protection layer on said lower wiring layer; forming said upper wiring layer on said organic SOG layer without processing of etching back; forming a via hole through an etching process by using a patterned resist layer provided on said upper wiring layer as a mask; performing ashing process with a plasma by making ion or radical which is induced from oxygen gas as a main reactant, under an atmosphere of pressure ranging from 0.01 Torr to 30.0 Torr; and burying said via hole with conductive material so as to electrically connect between said lower wiring layer and said upper wiring layer.

Abstract: A method for forming a dual gate of a semiconductor device includes the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain; and diffusing the impurity ions from the low re

Abstract: A method for forming logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate separating at least one logic area and at least one memory area. Gate electrode stacks comprising a polysilicon layer, a silicide layer, a first oxide layer, and a first nitride layer are formed in the device areas. The semiconductor substrate and the gate electrode stacks are covered with a first mask. The first mask in the logic areas is partially removed to expose the first nitride layer. The first nitride layer is removed to expose the first oxide layer in the logic areas. The first mask is removed. Processing continues to form LDD regions, S/D regions in the logic areas, and memory devices in the memory areas. Since the first nitride layer in the logic areas has been removed, an etching with an etch stop at nitride can form metal contacts in the logic areas and memory areas simultaneously.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials.

Abstract: An apparatus and methods for testing a semiconductor integrated circuit are disclosed. One embodiment includes a method for making a pass/fail determination in a semiconductor integrated circuit device. The method includes executing a test on the device after assembly and determining a pass/fail state of the device in response to the test. The method further includes programming a test history fuse on the semiconductor integrated circuit device to store a pass/fail state of the device. Another embodiment further includes performing a final test on the device, wherein if the stored pass/fail state indicates a pass state, a reduced final test is executed. A semiconductor integrated circuit device including internal circuitry, self test circuitry, and test history fuse circuitry is also disclosed.

Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A method of fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the substantially smooth anti-reflective coating is to be deposited. The anti-reflective coating may be a dielectric anti-reflective coating (DARC) which includes silicon, oxygen and nitrogen, and is preferably of the general formula SixOyNz, where x equals 0.40 to 0.65, y equals 0.02 to 0.56 and z equals 0.05 to 0.33. Preferably, x+y+z equals one. The method may also include fabricating a silicon nitride layer over the anti-reflective coating. A semiconductor device which includes a silicon nitride layer over an anti-reflective coating that has been fabricated in accordance with the inventive method has a density of less than about 40,000 particles or surface roughness features in the silicon nitride of about 120-150 nanometers dimension per eight inch wafer.

Abstract: The present invention provides a highly reliable polycrystal silicon thin film transistor with N2O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon. Also, the present invention provides a method of fabricating EEPROM or flash memory using N2O plasma oxide as a tunnel oxide, and N2O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device.

Abstract: A method for fabricating a micromachined structure. The method includes forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate, directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer, and directionally etching a portion the substrate exposed by the upper etch-resistant layer with a deep reactive ion etch.

Abstract: A method to implant NMOS polycrystalline silicon in embedded FLASH memory applications is described. In the method the polycrystalline silicon region (130) that will used to form the gate electrode of the NMOS transistor is doped simultaneously along with the source line in the FLASH memory array.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.