Abstract: In a computer system, input strings to be translated are composed of characters selected from a first alphabet. According to a predetermined criterion, a list of sub-strings is selected from the input strings to form entries in a dictionary. The entries of the dictionary are arranged according to a collating order of the first alphabet. An interval including the sub-strings of the input strings is partitioned into an all-inclusive and disjoint set of ranges. The sub-strings of the interval are arranged according to the collating order of the first alphabet, and each sub-strings of a particular range has a common prefix, the common prefix selected from the list of sub-strings. A unique encoding is assigned to each common prefix, the corresponding set of unique encodings composed of characters selected from a second alphabet. The input strings are parsed, one at the time, into a plurality of tokens, each token corresponding to a sub-string selected from the dictionary.

Abstract: In a decoding system which decodes a transmitted signal encoded by using a Reed-Solomon code, an error locator polynomial of the nth iteration is calculated based on a predetermined number of syndrome values; a group of variables of the (n-1)st iteration including a discrepancy and an error locator polynomial thereof; and an error locator polynomial of the (n-2)nd iteration. The method for providing the error locator polynomial comprises the steps of calculating a discrepancy of the nth iteration based on the syndrome values and the error locator polynomial of the (n-1)st iteration; calculating a temporal term based on the discrepancy of the (n-1)st iteration and the error locator polynomial of the (n-2)nd iteration; determining a correction term based on the temporal term and the discrepancy of the nth iteration; and computing the error locator polynomial of the nth iteration based on the correction term and the error locator polynomial of the (n-1)st iteration.

Abstract: An image coding device for coding an input image of multi-level. In the image coding device, an input multi-level image is analyzed by an image analyzing portion, and update information to be used when a probability estimation value is generated is generated by an update value determining portion on the basis of adjoining pixel information as a result of the analysis by the image analyzing portion. Further, a probability estimation value is generated by a probability estimating portion on the basis of the update information generated by the update value determining portion and the result of the analysis by the image analyzing portion, and the input multi-level image is arithmetically coded by a code word generating portion on the basis of the probability estimation value generated by the probability estimating portion.

Abstract: A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).

Abstract: A digital absolute position encoder is provided for determining absolute position of a first member with respect to a second member. The absolute position is determined within a resolution cell of L/2.sup.n, where n is an integer and L is a predetermined span. One of the members has a plurality of, m, tracks of binary indicia distributed over the predetermined span, L, where m is an integer less than n. The other member has a plurality of indicia detectors disposed on the second member for detecting the binary indicia. With such an arrangement, an encoder is provided having "a unit-distance code", yet uses less tracks than that used with a conventional Gray code encoder. Further, the encoder has a reduced number of transitions than that required on the track used with a conventional Gray code encoder. Both of these features simplify the design and fabrication for a given encoder resolution.

Abstract: An analog-to-digital converter mainly comprises an analog-to-digital conversion unit which produces a digital output, as an equivalent of an analog input supplied thereto, by performing a successive approximation. Herein, an instantaneous value of the analog input is compared with a reference signal so as to determine the digit in each of the bits of the digital output. The analog-to-digital converter can further comprise an analog comparator, an analog amplifier and a digital attenuator in order to reduce an effect of the noise. The analog amplifier amplifies the analog input by a gain so as to produce an intermediate analog signal. The analog-to-digital conversion unit converts the intermediate analog signal into an intermediate digital signal. The digital attenuator attenuates the intermediate digital signal by an attenuation rate so as to produce the digital output.

Abstract: A hybrid filter bank analog-to-digital converter includes continuous-time analysis filters and discrete-time synthesis filters. The continuous-time analysis filters partition a continuous-time wideband input signal into continuous-time subband signals. An analog-to-digital converter bank quantizes the subband signals at a low data rate. A bank of upsamplers increases the data rate of the quantized subband signals. A bank of discrete-time synthesis filters processes the upsampled subband signals, generating signals which are the discrete-time approximation of the continuous-time subband signals. The subband signals may be recombined into a discrete-time wideband signal which is the discrete-time approximation of the continuous-time wideband input signal. The linearity errors, analog-to-digital converter mismatches and quantization noise are not compounded between the frequency bands, thereby increasing resolution.

Abstract: A superconducting integrated circuit that uses a digital input to rapidly select any one of several thousand quantized output voltages. The voltages are generated directly by microwave synchronized Josephson junctions and are as accurate as the externally generated microwave frequency. The circuit makes possible fast voltage comparisons and the digital synthesis of ultra-accurate ac waveforms whose amplitude derives directly from the internationally accepted definition of the volt.

Abstract: A converter for converting an analog signal into a digital representation having a most significant bit (MSB), upper-significant bits (USBs), and lower-significant bits (LSBs) with a least significant bit being a predetermined incremental voltage value. The converter is responsive to external signals and is adapted to receive a supply voltage. The analog-to-digital converter provides for a determination of the most significant bit (MSB) that does not rely on the ratio factor between the capacitors of the charge-storage capacitor bank nor on the accuracy of the ratio factor of the resistors of the voltage-scale resistive ladder network.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read. A one-half clock cycle reset occurs at the start of every MSB comparison for every n-bit read, and this reset goes to every component in the A/D except the latch for the LSB, which must be held for at least one more clock cycle before since it has not yet been output to the data bus as yet.

Abstract: A decoder has first and second decoder circuits for producing dual sets of outputs. The first decoder circuit is responsive to input lines B.sub.1 -B.sub.n representative of a binary value x and has first outputs Z.sub.1 -Z.sub.m where m=2.sup.n. In response to the value x applied to the first decoder, output line Z.sub.x+1 is set high while the remainder are set low. The second decoder circuit comprises m transmission gates serially connected between a first and a second potential. The transmission gates are each directly driven by a respective one of said first outputs Z.sub.1 -Z.sub.m. The second decoder circuit generates second outputs Y.sub.1 -Y.sub.m-1 at junctions of the transmission gates. In response to the value x applied to the first decoder, x number of the outputs Y.sub.1 -Y.sub.m-1 are set high beginning with the least significant output Y.sub.1 and continuing consecutively up to the output Y.sub.x with the remainder being set low.

Abstract: A method and apparatus for improving the performance of coding systems in the presence of frame erasures or lost packets. The encoded signal is modified after transmission but prior to decoding by a decoder preprocessor. The preprocessor recognizes that a given frame has been corrupted and modifies the encoded signal so that the decoding thereof will result in improved coding system performance. Specifically, based on the decoding process and on a predetermined target signal, the encoded signal is modified so that the decoding thereof will generate an approximation to the target signal. In a first illustrative embodiment, a CELP speech coder is used and the target signal is an excitation signal comprised of all-zero excitation vectors. In this case, the portion of the corrupted excitation signal indices which identify the corresponding gain factors are set to values which represent a low gain factor.