Abstract: A pipelined multi-stage analog-to-digital converter (ADC) exhibits high speed and high resolution characteristics in a small chip area using a CMOS process. An optimized high resolution multi-stage ADC improves integral non-linearity errors (INL) and differential non-linearity (DNL) errors and hence increases yield. A binary-weighted capacitor array is used in a multiplying digital-to-analog converter (MDAC) in a front-end stage, and a unit capacitor array is used in the MDACs of the latter stages thereof. Offset, feedthrough and gain errors are removed via digital correction. A digital calibration technique is adopted to reduce the non-ideal effects resulting from component mismatch, by measuring all the code errors of the front-end stage, to thereby minimize the midpoint code DNL error without reference to code symmetry.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons the determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read.

Abstract: Method for determination of time errors in connection with analogue-digital conversion of quadrature detected signals by feeding a special, periodically repeated signal, the frequency of which is changed during each period, to the device whose time errors are to be determined. The special signal is quadrature detected, whereby two quadrature components (I and Q) are formed. The quadrature components are sampled and the samples are converted to digital form, whereby each of the quadrature components are sampled at at least two fixed points of time for each period of the special signal. The samples from a number of periods of the special signal related to the fixed points of time are Fourier transformed in order to generate spectra in which expressions are contained which describe both the fundamental tone of the special signal and its image tone.

Abstract: In an image encoding apparatus, image information is quantized and variable-length encoding is performed thereon so that the data are stored in a buffer. Thereafter, the data in the buffer are transmitted to the outside at a fixed data rate. At this time, a controller monitors a number of occupied bits in the buffer, and when the number of occupied bits is not more than predetermined thresholds, the controller switches the output of the apparatus to a dummy data generator. At this time, a parameter which is used for rate control is initialized, and dummy data which can be eliminated at a decoding circuit are outputted from the dummy data generator. Furthermore, bit allocation is changed so that a sum of the number of occupied bits and the bit allocation to a frame, which is determined before encoding, does not exceed a fixed amount. Moreover, when the number of occupied bits exceeds the fixed value, a quantization step size is changed to a greater value.

Abstract: An N-bit analogue-to-digital converter can increase the resolution by 3 bits, by very precise coding of the differential phase at the output of the electro-optic phase modulator controlled by the electric signal to be converted. The optical signals obtained are processed by an electro-optic device that outputs electric signals that are functions of the sine and cosine of the phase. A coding device uses the symmetry of the trigonometric circle partitioned into four consecutive sectors between 0 and 27.pi. in order to convert the absolute values of the electric signals obtained on (N-3) bits, independently of the home sector of the phase. A transcoding device uses the value of the sine and cosine coded on (N-3) bits, to output a value V of the electric signal, on N bits, as a function of the home sector.

Abstract: A multiplexed delta-sigma modulator for performing analog to digital conversion on a plurality of input analog signals. These input analog signals are input to a multiplexer, where the input analog signals are converted into a single, time-division multiplexed analog signal. The time-division multiplexed analog signal is then received by the delta-sigma modulator, which oversamples the input signal and outputs a time-division multiplexed digital signal. The time-division multiplexed digital signal is then sent to a decimator which outputs a time-division multiplexed digital signal at a rate corresponding to the Nyquist rate of the input analog signals.The signal is sent from the decimator to a first down-sampler, and then to a demultiplexer, where the time-division multiplexed, decimated signal is sent to the appropriate output port of the demultiplexer at a sequential rate corresponding to the sequential rate utilized by the input multiplexer.

Abstract: A sigma delta convertor 20 has a number of time slots that are programmable connectable to the input channels 200 via a multiplexer 205. Conversion throughput of any one input channel is increased by connecting two or more time slots to the input channel. For an eight input channel embodiment 800 the throughput of conversion of one input can be increased 2.times., 4.times. or 8.times. by connecting, respectively, 2, 4 or all 8 time slots to the selected input channel.

Abstract: Systems and methods for compressing data. Lempel-Ziv data compression is applied in the context of an exhaustive sliding window implementation using a large character history bit pattern memory. Shifted updating of the character history bit pattern memory is accomplished through a pointer system. Linear patterns of bits, derived by COPY function from the character history bit pattern memory or by bit wise AND logic combination of selected bit patterns, are circularly shifted in synchronism with new data characters using a toroidal bit shift register. The relatively long bit strings subject to shifting are converted to a matrix format, shifted with fewer affected bits and returned to a linear format. The systems and methods materially improve the speed of exhaustive sliding window data compression as accomplished by general purpose processors.

Abstract: A method of accurately recording and reproducing an analog signal having a wide dynamic range with a small amount of information first samples amplitude values of an analog waveform which are then converted to a digital signal. Plural frames of data are stored in a buffer circuit. For each frame, the differences between successive values of the digital signal are extracted to form a second digital signal having an amount of shift S common to one frame, which is established and stored in a memory. In response to the amount of shift, the second digital signal is shifted toward lower bits thereof to compress the second digital signal into a third digital signal having less bits which is stored. When the difference values are small, the amount of shift is reduced to suppress errors produced during compression. When the difference values are large dynamic range is obtained, thereby coping with great signal variations without neglecting small variations in the analog signal.

Abstract: An analog to digital converter which includes a resistive network for generating a number of first reference voltages related to each other by a first linear relationship and a number of second reference voltages related to each other by a second linear relationship, where the first linear relationship is different from the second linear relationship. Also included are first comparators which compare an analog signal to each one of the first reference voltages to produce specified first comparator signals where a respective comparator of the first comparators is provided for each of the first reference voltages. Second comparators are provided to compare the analog signal to each of the second reference voltages to produce second comparator signals where a respective comparator of the second comparators is provided for each one of the second reference voltages.

Abstract: A method and apparatus generates a channel codeword based on codewords with arbitrary block digital sums. Respective portions of the channel codeword are generated based on respective sets of input symbols, and the channel codeword is generated from the portions in accordance with another set of input symbols. The potions are advantageously codewords, comprising symbols, generated by selecting, for each set of input symbols, a codeword from a codebook and by adapting, as for example by ordering or by inverting symbols in, the codewords to form the channel codeword.

Abstract: A micropower analog-to-digital converter (ADC) for use in an implantable medical device is disclosed. The ADC achieves a high conversion speed at micropower levels through a number of timing and circuit improvements over the conventional implementation of the successive approximation ADC architecture. The ADC includes a digital-to-analog converter (DAC) that preferably is implemented as a binary-weighted, switched capacitor array that employs top plate charging and performs bipolar conversion. The DAC provides an analog output signal representing array charge to a comparator. During a comparator latch phase, the DAC asynchronously determines a bit of the ADC digital output signal in response to the comparator output, and initiates a test of the next least significant bit during the same latch phase. Further, the DAC analog output signal is timed to settle during the latch phase in response to both the bit update and the next bit test.

Abstract: A D/A converter (10) converts a digitized analog signal (32) to an analog signal (50). The D/A converter (10) includes first filtering stage (12), second filtering stage (14), and reduced-bit D/A converter (16). The first filtering stage (12) operates at a first sampling rate (25), interpolates the digitized analog signal (32) from an initial sampling rate to a first sampling rate (25), performs an anti-alias filter, and performs a first comb filtering function. The second filtering stage (14) operates at a second sampling rate (46), interpolates the digitized analog signal (32) to the second sampling rate (46), performs a second comb filtering function, and performs a noise shaper filter to produce a reduced-bit second sampling rate signal (48). The reduced-bit D/A converter (16) converts the second sampling rate signal (48) to an analog signal (50).

Abstract: In a control circuit including an A/D converter, a parallel-to-serial input buffer, a parallel input buffer, a serial-to-parallel output buffer and a parallel output buffer which are built in a chip, provided with a microcomputer, an A/D conversion is carried out by controlling a time of an A/D conversion conducted by the A/D converter correspondingly to a condition of an output port of the output buffer, thereby preventing an A/D converted value from being affected by an inversion in the output of the buffer.

Abstract: An efficient encoding/decoding apparatus of this invention comprises orthogonal transform element (10) for orthogonally transforming a digital signal obtained by allowing an analog signal to undergo analog/digital conversion, quantizer (11) for quantizing the digital signal which has undergone orthogonal transform processing, inverse quantizer (21) for inverse-quantizing a digital signal which is not yet caused to undergo inverse orthogonal transform processing, and inverse orthogonal transform element (20) for inverse-orthogonally transforming the orthogonally transformed digital signal, wherein rounding in even number direction or rounding in odd number direction is used in at least one of the orthogonal transform processing and the inverse orthogonal transform processing. Thus, accumulation of rounding errors at the time of, e.g., such a direct digital dubbing to repeatedly encode/decode digital signals such as video signals, etc.

Abstract: A level-controlling unit consisting of an inverter controls a level of a given pulse signal, the level controlling being performed in a predetermined manner. An analog-signal producing unit consisting of a low-pass filter produces an analog signal by integrating the pulse signal having undergone the level controlling. An analog-signal processing unit consisting of A-D converter processes the analog signal with a dynamic range thereof so as to supply a digital signal, the dynamic range being defined by a predetermined reference level. The predetermined manner is such that a substantial possible level variation extent of the analog signal received by the analog-signal processing unit corresponds to the dynamic range.

Abstract: A set of independent pseudonoise (PN) component codes greater than two are combined in a manner which produces one or more I and Q uncorrelated orthogonal pairs of resulting combined PN sequences. At least two of the component codes in a resulting combined PN sequence are combined in a manner which produces an overall imbalance of ones and zeros in the binary expression of the resulting combined PN sequence so that the resulting composite code has a partial correlation with a predetermined one of the PN component codes. In the preferred embodiment, three component codes are combined to produce uncorrelated orthogonal pairs of composite codes wherein at least one of the pairs of composite codes is produced to have a partial correlation with one or more of the component codes.

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: A successive approximation circuit and method are disclosed for digitally approximating a moving signal using an analog-digital converter (ADC) and a comparator for generating a comparison signal from the moving signal. An estimate register and a bit and conversion control circuit are provided, with the bit and conversion control circuit including a bit control circuit and a conversion control circuit, where the bit control circuit adjusts a current plurality of output bits to compensate for an error due to a slew rate to generate the digitally approximated moving signal. An adder is included for adding the control value to the current plurality of output bits to generate the next plurality of output bits. Alternatively, an adjustment selection circuit and a logic chain circuit are included.

Abstract: A coder/decoder selects one of a set of look-up tables for encoding/decoding a symbol. Each look-up table contains boundary values that result from an arithmetic coding model partitioning a first interval. A second interval contains an arithmetic code. During encoding, look-up table entries for a symbol value are converted to the scale of the second interval. The scaled values indicate a smaller interval containing the arithmetic code. Code bits are generated when most significant bits of upper and lower scaled values are equal. During decoding, a code word, which is a part of an arithmetic code, is normalized from the scale of the second interval to the scale for a look-up table and then compared to entries of the look-up table. When a segment containing the code word is identified, a decoded symbol value is known. A scaling circuit converts boundary values for the segment to the scale of the second interval then changes the second interval.