Abstract: Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier.

Abstract: An improved method and apparatus for transmission of dual 4-wire analog data services between a telephone company location and a subscriber premises over a single twisted pair, providing a 4:1 pair gain. In a preferred embodiment the invention provides for method and apparatus for transmission of multiple analog data signals for dual 4-wire analog data services over a single twisted pair from telephone company equipment to a subscriber, using 2B1Q or 4B3T digital signals.

Abstract: According to the present invention, for encoding input signals, the input signals are transformed into frequency components, and the frequency components are separated into a first signal composed of tonal components and a second signal composed of other components. The first and second signals are encoded respectively, and code strings for transmission or recording are generated on the basis of encoded signals resulting from first and second encoding. For example, only the first signal is encoded and the code string is caused to include partial information strings grouped so as to have common values on the basis of at least one of reference parameters pertaining to the signal separation and parameters pertaining to the first encoding. Thus, more efficient encoding than in the conventional technique can be realized.

Abstract: An N-bit A/D converter comprises 2.sup.N cells connected in cascade, wherein the start cell receives an input analog signal and each cell performs a determination operation to produce a determination signal. Each cell comprises a sample and hold circuit, a comparator, and a subtracter. The sample and hold circuit samples an analog value from a first analog signal received from a previous cell and holds the analog value. The comparator compares the analog value with a reference value to produce the determination signal. The subtracter subtracts a subtrahend value from the analog value to produce a second analog signal which is received by a next cell. The next cell receives the output of the cell as the above-mentioned first analog signal and performs the same determination operation as the cell. The cascade-connected cells are controlled with timing clocks so as to perform a pipeline operation such that the cell produces the determination signal when the next cell receives the second analog signal.

Abstract: In a method of improving a distortion ratio of an analog-to-digital converter, an analog signal to be digitized is additively superposed with a band-limited noise signal. The thusly produced sum signal is supplied to the analog-to-digital converter for sampling and quantization.

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage.The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: The AD conversion control section of the processor sets the clock generating circuit of the output port alternately to an L-level output condition and an H-level output condition to generate a clock signal. A chip select signal is caused to be output from the chip select circuit of the output port in synchronization with output of the first clock signal by the interruption signal. Furthermore, the bit data output in series bit by bit from the AD converter in synchronization with occurrence of a clock signal is incorporated bit by bit in synchronization with the interruption signal from the input ports to be stored in the register.

Abstract: This invention discloses a versatile power and control circuit for an electric door strike that is operable in four different modes with readily adjustable release times. In addition, the invention is directed toward the provision of a highly efficient power supply that permits miniaturization and prevents overheating in the confined space that is available for installation in a door jamb.

Abstract: A variable length coding process encodes a string of symbol values using arithmetic coding models selected according to the syntax of the string. The arithmetic coding models are optimized for each separate symbol in the string to provide efficient coding that provides a shorter average code length than is provided with arithmetic coding using a single model. In an embodiment for moving image coding, two sets of arithmetic coding models, one for intra frames and one for inter frames, are used for a series symbols representing DCT blocks. The model used for a symbol depends of the symbol's value and order in the series.

Abstract: A method and apparatus detects whether more than one object has been selected from a set of objects. A unique code and an error code is coupled to objects in the set. At least one object is selected and the unique codes from the selected object are logically summed, as are the error codes from the selected objects. A test code is generated from the logically summed unique code and tested for equality with the logically summed error code to determine if more than one object was selected.

Abstract: A data format converter for executing log conversion, antilog conversion, floating point conversion and inverse floating point conversion in an adaptive differential pulse code modulation (ADPCM) processor, which has an excellent data format conversion speed.

Abstract: A sensor failure detection circuit for a position encoder, the sensor failure detection circuit receiving from a first set of at least one position sensor position signals which change state at a high resolution and from a second set of at least one position sensor position signals which change state at a lower resolution, the detection circuit monitoring a count for the position signals at the high resolution between states of the position signals at the lower resolution and comparing the count with a predetermined range which represents an expected count for the position signals at the high resolution between the states of the position signals at the lower resolution.

Abstract: A variable length code(VLC) decoding apparatus for simultaneously decoding two different VLC bit streams includes two storage units, in response to each read signal, for storing fixed length segments contained in each of the VLC bit streams; a first switch for selecting the fixed length segments from a first or a second storage unit, and for selecting a first or a second window control signal; a barrel shifter in response to selected window control signal for forming a decoding window on the selected segments in order to produce a decoding window output sequence thereof; a memory for producing a decoded word in response to a variable length codeword and for producing a codeword length output; a second switch, in response to a second selection signal, for producing the decoded word and the codeword length output as a first decoded word and a first codeword length or a second decoded word and a second codeword length output; two accumulators, in response to each of the codeword lengths, for generating the two w

Abstract: Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.

Abstract: A DAC deglitch circuit comprising a switch circuit for grounding the DAC output during the DAC's transitional period. The DAC is preferably a current type, although a voltage type is also contemplated. The switch circuit preferably includes a biased transistor circuit receiving the update or hold signal for grounding the output of the DAC during the hold period. The deglitch circuit generally causes a consistent glitch at every transition, which is easily filtered out by a filter circuit. The deglitch circuit is very simple inexpensive and consumes very little space and power.

Abstract: Fixed-length segments of a variable-length encoded (VLE) bitstream are used as indices into a lookup table. The current table entry is interpreted to determine how many complete VLE signals are in current bitstream segment. If the segment contains one or more complete VLE signals, then the corresponding decoded signals are retrieved from the table entry. Otherwise, if the segment contains no complete VLE signals, then special processing is performed to decode the segment.

Abstract: An associative memory is utilized to perform LZW data compression. The respective locations of the memory contain a prefix code field and a character field. A register containing a code field and a character field is associatively compared to the locations of the memory to determine if a match exists therewith. If a match is found, the address of the match is inserted in the code field of the register and the next input character is inserted in the character field thereof. This process is continued until no match occurs. The code existing in the code field of the register is transmitted as the compressed code of the string and the contents of the register is written into the next empty location of the memory. A next cycle is initiated by nulling the code field of the register and repeating the described steps.

Abstract: A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

Abstract: A variable length decoder device receives a stream of variable-length encoded data segments for successive transient storage. The storage is recurrently accessed under control of successive pointers. A decoder is fed by the storage and decodes a stream of data segments each from a respective encoded data segment. Furthermore, in step with the decoding a next pointer is produced as being directly derived from the accessing through reading of a localizer information. The latter again is produced in a preprocessor that sits before the storage, through localizing the data segments and indicating each segment by an associated localizer.

Abstract: A system and method for compressing or predicting data information received within an input stream, wherein contextual information is utilized in the selection of dictionaries for encoding or predicting of a next phrase within the information stream. The present invention utilizes contextual information in conjunction with dictionary-based Lempel-Ziv compression processes.