Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code is disclosed. The analog to digital converter has a voltage reference generator to create a plurality of voltage references that divides the total conversion range of the input into increments equal to the smallest resolution increment. The digital output code is divided into most significant bits, intermediate significant bits and least significant bits. The most significant bits are encoded from a set of coarse digital signals that are formed in a set of coarse comparators. The coarse digital code is used to determine the selection of the sub-coarse voltage references. The intermediate significant bits are encoded from a set of subcoarse digital signals. The subcoarse digital code that and the coarse digital code are used to determine the selection of the fine voltage references.

Abstract: A noise cancelling circuit (10) is used with a D/A converter, the converter including a first modulator (11) and a data output. The circuit (10) has an error measuring arrangement (12, 13, 14) for measuring a quantization error signal of the modulator (11). A filter (19) receives the error signal end provides a fired error signal. A filter compensator (17) is coupled to the data output and provides a compensated output. A scaler (15) is coupled to receive the filtered error signal and provides a scaled filtered error signal. A second modulator (16) is coupled to receive the scaled filtered error signal and provides a single bit stream of error data. A summing arrangement (18) sums the single bit stream of error data and the compensated output from the first modulator and provides a corrected output, such that the error signal is filtered, sealed and modulated end the data output is compensated such that the corrected output is obtained having a substantially reduced quantization error.

Abstract: A DAC is disclosed that includes a decoder having output lines corresponding to digits of digital data. The decoder generates an output corresponding to the value of the digital data on the output lines. The DAC further includes a constant current source, and output means connected to the constant current source for providing an output voltage by a flowing current. The DAC also has driver transistors, where each transistor is connected to one of the decoder output lines and to the constant current source. The output means conducts a current from the constant current source when the connected output line is activated. Current limit transistors are each connected to each one of the driver transistors. The decoder output lines are grouped so as to correspond to each of the ranges of a gamma compensation curve. A common reference voltage for each group is applied to a control terminal of the current limiting transistors associated with the output lines in each group.

Abstract: A folding amplifier is proposed for the construction of an A/D converter to which a current signal is fed as the input signal and from which a current difference signal is derived using a reference current. This current difference signal is fed to a first current-controlled current source, which is designed as a current mirror, and also to a second current-controlled current source, whereby the first current source takes over this current when the current difference signal has a positive sign and if the current difference signal has a negative sign the second current source takes over this current. The outputs of the first and second current-controlled current sources are fed to the output of the folding amplifier. Preferably, this folding amplifier is provided with a third current-controlled current source with sign reversal whose input is connected to the outputs of the first and second current sources and whose output is a V-shaped output current signal.

Abstract: A static eliminator for eliminating static electricity between the human body and a charged object or from the charged object itself. Static electricity is introduced from a charged object into a discharger for discharging the static electricity by an electrical discharge and an exothermic device for eliminating the static electricity as heat. Thus, static electricity is consumed by electrical discharge and generation of heat.

Abstract: An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74).

Abstract: The present invention provides a plurality of code tables such as a high-usage code table and a low-usage code table in an entropy coding unit, and transforms a block-sorted last character string from a block-sorting transforming unit into an MTF code string in an MTF transforming unit. The entropy coding unit switches the code tables at a discontinuous part of the MTF code string to perform entropy coding. In addition, the present invention stores reference lists, whose number is equal to the number of kinds of used characters, in a reference list memory. The MTF transforming unit selects a reference list corresponding to a first character of the block-sorted character string to perform an MTF transformation.

Abstract: Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.

Abstract: A digital signal decoding apparatus for preventing errors which cannot be corrected sufficiently by error correction from reflecting on a decoded signal. An uncorrectable error part of a digital signal or a data part including the error part is replaced with a special code including a synchronous code, and is output to decoding means. Because the decoding means capable of identifying the synchronous code can also identify the special code, a proper error processing can be executed by confirming the presence of errors at the time of decoding. Therefore, by using the decoding means, it is possible to prevent errors which cannot be sufficiently corrected from reflecting on a decoded signal.

Abstract: A priority encoder for encoding input data by scanning the input data in a predetermined direction, includes: a first voltage section for charging a plurality of output lines to a first voltage level; a plurality of switching elements connected to the plurality of the output lines, each of the plurality of switching elements being turned on in accordance with a value of the input data; and a second voltage section for charging a selected one of the plurality of output lines to a second voltage level different from the first voltage level, through the switching elements which are turned on.

Abstract: A conversion characteristic test circuit and method for an A/D converter uses a DNL error, an INL error, and a dynamic conversion characteristic to analyze digital data output from an A/D converter for judging an operation state of the A/D converter. The conversion characteristic test circuit includes a data detecting unit that detects a digital code randomly output from the A/D converter. A test signal generating unit generates a sequential test signal in accordance with a test clock signal. A DNL error data detecting unit receives a data output by the data detecting unit in accordance with the sequential test signal and subtracts the data from an code-by ideal data to compute DNL error data. An INL error data detecting unit computes INL error data based on the DNL error data and the test clock signal. A judging unit receives the outputs of the DNL error data detecting unit and the INL error data detecting unit and detects a DNL error and an INL error to judge an operation state of the A/D converter.

Abstract: A pulse-width-modulated digital-to-analog converter is responsive to a digital control value for switching between a high gain mode and a low gain mode. The converter includes a free-running rollover counter, a reference register and a comparator. Pulses from a comparator are split into two paths, one path including a switch, and fed into a plurality of resistive elements connected connected to a common output node. Depending on the state of the switch, the network's output value will either follow its input or be a fraction thereof, without change of duty cycle or output impedance. The output node may be connected to a capacitive element to form a low pass filter for generating an analog waveform.

Abstract: An encoding and decoding system that includes a model implemented hardware or software that is capable of operating on arbitrary data (e.g., data of a different or variety of types.) The model generates a context and binary decision for each symbol, which a binary entropy coder that uses to generate a compressed bit stream. One context model is operable with arbitrary data and uses context bins of various orders to generate a context and a decision for each symbol in an input symbol stream. An entropy coder estimates probability and generates compressed data stream in response to contexts and decisions from the model and according to generated probability estimates.

Abstract: A variable-length code decoding apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence and a code value in response to a decoded codeword length, a relay circuit for latching the second window output sequence for one-half the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a second look-up table memory for producing a fixed-length word in response to the decoded codeword length and the code value, and an accumulation block for producing the window control signal.

Abstract: A run-length decoding apparatus, for use in a video signal decoding system, for decoding a run level coded video signal to provide decoded video signal comprises an address generator, receiving the run data, for generating a write address denoting a memory location for storing the level data, a counter, responsive to a clock signal, for generating a read address for sequentially addressing the memory locations from an upper most memory location to a lower most memory location, and memory, having a number of memory locations, for storing the level data based on the write address, and for generating the decoded data stored in the memory locations based on the read addresses to thereby provide the decoded video signal.

Abstract: A position detecting device and a position pointing device thereof, which are capable of transmitting much information at high speed without lowering the sampling rate of coordinate detection. The position pointing device controls the resonance characteristic of a resonance circuit to one of at least four different resonance characteristics in accordance with at least two bits of binary code out of a plurality of bits of binary code, which represent pointing device information, at a preselected timing. A tablet detects the resonance characteristic of the resonance circuit by resonance characteristic detecting means from an electric wave generated from the resonance circuit at the preselected timing and converts it into at least two corresponding bits of binary code, thus enabling the transmission of information of two bits or more at a time.

Abstract: A high-speed multiplexing technique employs diode bridges to multiplex the outputs of two or more digital-to-analog converters (DACs) together. Like prior art techniques, the diode bridges isolate the DAC outputs from one another and are activated by forward biasing the bridges, one at a time in a staggered-phase, sequential fashion with sequenced biasing currents, to effectively connect the DACs, one at a time to an output signal. Unlike prior art techniques, however, the low capacitance diodes are inserted in series with the sequenced biasing current driving each diode bridge, one on each side of the bridge. The low capacitance diodes are oriented to pass current in the direction of forward bias of the diode bridges. Voltage mode switching is employed to limit the effect of parasitic capacitances on output amplitude. One embodiment is directed to a pair of back-to-back diode bridges driven by a single transformer secondary winding.

Abstract: A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator.

Abstract: A variable length code decoding apparatus stores a 2.sup.n -bit variable length coded serial input bit stream, n being a positive integer, and, in response to a control signal, outputs in parallel an objective bit stream having a predetermined number of bits and decodes the objective bit stream from the interface means and outputting a decoded symbol together with its codeword length data. A variable length code decoding apparatus compares the codeword in the objective bit stream and the decoded symbol with the variable length data in the table and generates the control signal.

Abstract: An N valued input symbol is encoded by using a tree structured binary arithmetic coder wherein N is an integer larger than 2.sup.M-1 but not greater than 2.sup.M with M being a non-negative integer. First, the input symbol is converted into M bits of binary symbols. Thereafter, a context for a kth bit of the binary symbols is selected among a kth groups of contexts, each of the contexts in a group representing a different probability model of a binary symbol. The kth group of contexts includes 2.sup.k-1 contexts therein and a larger value of k represents a lower bit of the binary symbols, k being an integer from 1 to M. A context corresponding to an Lth bit is selected among an Lth group of contexts based on one or more upper bits thereof, L being an integer ranging from 2 to M. Finally, each of the M bits of the binary symbols is encoded serially based on its corresponding context by using a binary arithmetic coding method.