Patents Examined by Jay C Chang
  • Patent number: 11075354
    Abstract: A display panel is provided. The display panel includes a substrate, an active component disposed on the substrate, a passivation layer covering the active component, a planar layer covering the passivation layer, a first electrode disposed on the planar layer, a pixel defining layer covering the first electrode and the planar layer, an insulating layer disposed on the pixel defining layer, a conductive layer disposed on the insulating layer, an electroluminescence layer, and a second electrode. The first electrode is electrically connected to the active component by extending through an opening disposed in the passivation layer and the planar layer. The insulating layer covers a part of the pixel defining layer. The electroluminescence layer is disposed between the first electrode and the second electrode. A thickness of the electroluminescence layer is larger than or equal to a thickness of the insulating layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Jia Tang
  • Patent number: 11069717
    Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11063116
    Abstract: A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates (9,19a,19b,19c). An inner end of the field plate (19c) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate (19b) of the high-voltage N-ch MOS located closest to the low-side circuit region.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 13, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Manabu Yoshino
  • Patent number: 11063225
    Abstract: A highly reliable light-emitting element having high emission efficiency is provided. The light-emitting element includes a light-emitting layer including a first organic compound and a guest material. The first organic compound has a substituted or unsubstituted carbazole skeleton. In the light-emitting layer, the weight ratio of a hydrocarbon group substitution product in which at least one of hydrogen atoms in the first organic compound is substituted by a hydrocarbon group having 1 to 6 carbon atoms to the first organic compound is greater than 0 and less than or equal to 0.1.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 13, 2021
    Inventors: Takeyoshi Watabe, Satoshi Seo, Nozomi Komatsu, Ryohei Yamaoka, Harue Osaka, Kunihiko Suzuki, Shunsuke Hosoumi
  • Patent number: 11062999
    Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Koon Lee, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
  • Patent number: 11056441
    Abstract: An electronic module includes a circuit substrate including conductive pads interconnected by traces, including a ground pad for connection to an electrical ground. One or more electronic components are mounted on the circuit substrate. A housing including a dielectric material is mounted on the circuit substrate so as to cover the one or more electronic components. A metal lead, which has first and second ends, is embedded in the dielectric material such that the first end contacts the ground pad on the circuit substrate when the housing is mounted on the circuit substrate, and the second end is exposed at an outer surface of the dielectric material. A conductive coating is disposed over the outer surface of the housing in galvanic contact with the exposed second end of the metal lead.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 6, 2021
    Assignee: APPLE INC.
    Inventors: Colleen F. Mischke, Kayo Yanagisawa, Yazan Z. Alnahhas
  • Patent number: 11056564
    Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 6, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hong Wei, Chien-Hsiang Yu, Hung-Sheng Chen
  • Patent number: 11049825
    Abstract: A method for producing a semiconductor device of the present invention includes: step (I) of disposing one or more semiconductor elements each having an active surface, on a thermosetting resin film containing a thermosetting resin composition, such that the thermosetting resin film and the active surfaces of the semiconductor elements come into contact; step (II) of encapsulating the semiconductor elements disposed on the thermosetting resin film with a member for semiconductor encapsulation; step (III) of providing openings in the thermosetting resin film or a cured product thereof after step (II), the openings extending to the active surfaces of the semiconductor elements; and step (IV) of filling the openings with a conductor or forming a conductor layer inside the openings.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 29, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Aya Kasahara, Toshihisa Nonaka, Daisuke Fujimoto, Naoya Suzuki
  • Patent number: 11048023
    Abstract: An apparatus includes an array of metal nanowires embedded in a matrix of optically tunable material providing a tunable hyperbolic metamaterial, and a control circuit including (i) a current source coupled to first ends of the array of metal nanowires and (ii) a ground voltage coupled to second ends of the array of metal nanowires. The control circuit is configured to modify a state of the optically tunable material utilizing current supplied between the first and second ends of the array of metal nanowires to dynamically reconfigure optical properties of the tunable hyperbolic metamaterial.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Abram L. Falk, Damon Brooks Farmer, Jessie Carrigan Rosenberg
  • Patent number: 11049926
    Abstract: A stretchable display device according to an embodiment of the present disclosure includes a stretchable first substrate. A plurality of second substrates is disposed on the first substrate and spaced apart from one another, and the second substrates have a greater rigidity than the first substrate. A transistor is disposed on each of the plurality of second substrates, and a planarization layer is disposed on the transistor. A light emitting element is disposed on the planarization layer, and the planarization layer may have a reverse-taper shape. Accordingly, since the planarization layer has a reverse-taper shape in the stretchable display device according to an embodiment of the present disclosure, it is possible to be in direct contact with lines at a lower portion without specific configuration.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 29, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyunju Jung, Eunah Kim
  • Patent number: 11043548
    Abstract: A display apparatus includes a substrate including a bending area between a first area and a second area; a display unit provided over the first area of the substrate; and a wiring unit provided over the bending area and including a plurality of wirings crossing the bending axis, wherein each of the plurality of wirings includes a central wiring, at least one first auxiliary wiring, and at least one second auxiliary wiring, wherein the at least one first auxiliary wiring and the at least one second auxiliary wiring are alternately provided by partially overlapping each other.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ahram Lee, Seongsik Ahn, Minki Kim
  • Patent number: 11043421
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of cooling the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 22, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11037981
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 11037813
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and then picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11038036
    Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
  • Patent number: 11031434
    Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Wei Chuang Wu
  • Patent number: 11024744
    Abstract: Provided is a semiconductor device including: a gate electrode; a channel layer arranged in a region directly below or directly above the gate electrode; a source and a drain electrodes arranged to be in contact with the channel layer; and a first insulating layer arranged between the gate electrode and the channel layer, the channel layer including a first oxide semiconductor, the source electrode and/or the drain electrode including a second oxide semiconductor, the first and second oxide semiconductors containing In, W and Zn, a content rate of W/(In+W+Zn) being higher than 0.001 atomic % and not higher than 8.0 atomic %, a content rate of Zn/(In+W+Zn) being from 1.2 atomic % to 40 atomic %, an atomic ratio of Zn to W being higher than 1.0 and lower than 20000. Also provided is a method for manufacturing the device.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 1, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Miki Miyanaga, Kenichi Watatani, Hideaki Awata
  • Patent number: 11011671
    Abstract: A light emitting device includes: a light emitting element; and a light transmissive member bonded to an emission surface of the light emitting element; wherein the light emitting element and the light transmissive member are bonded via a bonding portion that comprises a portion of the light emitting element and a portion of the light transmissive member; wherein the bonding portion contains at least one rare gas element selected from the group consisting of He, Ne, Ar, and Kr; and wherein a peak of a rare gas element distribution is positioned away from the emission surface in at least one of the light emitting element and the light transmissive member.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 18, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Satoshi Shichijo, Harunobu Sagawa
  • Patent number: 11004820
    Abstract: An apparatus and method for filling a ball grid array template and a method for transferring a plurality of balls are disclosed. The apparatus includes a flat base, a plate and a stationary ball supply bin. The plate is mounted on the base and configured to be rotatable about a first axis perpendicular to the base. An upper surface of the plate includes a plurality of holes forming the ball grid array template. The stationary ball supply bin is mounted to the base. The base is configured to be inclined at an angle relative to a horizontal plane. The ball supply bin is configured in use to dispense a plurality of balls onto the corresponding plurality of holes forming the ball grid array template as the plate is rotated about the first axis.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 11, 2021
    Assignee: Aurigin Technology Pte Ltd
    Inventors: Boon Chew Ng, Ee Teoh Lim
  • Patent number: 11004875
    Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 11, 2021
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Catherine Ramsdale, Brian Hardy Cobb, Feras Alkhalil