Abstract: A semiconductor device has a substrate and encapsulant deposited over the substrate. An electrical connector is disposed over the substrate outside the encapsulant. An antenna can be formed over the substrate. A first shielding material is disposed over a portion of the encapsulant without covering the electrical connector with the first shielding material. The first shielding material is disposed over the portion of the encapsulant and the portion of the substrate using a direct jet printer. A light source emitting an ultraviolet light or intense pulsed light is directed at the first shielding material to induce sintering. A cover is disposed over the electrical connector. A second shielding material is disposed over the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps the first shielding material and covers a side surface of the encapsulant and a side surface of the substrate.

Abstract: A method for manufacturing a power transistor. The method includes: applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate, producing an expansion layer, which is situated inside the first epitaxial layer, producing various implanted areas starting from the front side of the semiconductor substrate, producing a trench structure starting from the front side of the semiconductor substrate, producing first isolation areas in the surroundings of the trench structure, producing transistor heads, and applying metal layers.

Abstract: A fan-out wafer-level packaging structure and a method for manufacturing it are disclosed. The structure includes: a rewiring layer, a chip, an electrical component, a protective layer made of UV-curable adhesive, a molding layer, and a solder ball. The protective layer is disposed on surfaces of the electrical component, sealing the electrical component, and ensuring its safe operation and reliability, mitigating risks of melting and spillage of solder in the electrical component, and preventing electrical shorts and delamination between molding layers and the electrical component. The protective layer is formed by UV-curing or UV/thermal-dual-curing, to prevent loss of upper portions of the adhesive resulted from the upper portions flowing downward after dispensing. A dual-curing process can further solidify the protective layer, enabling the protective layer to better seal and protect the electrical component.

Abstract: In one example, an electronic device includes a substrate including a substrate upper side and a conductive structure comprising substrate upper terminals adjacent to the substrate upper side. Vertical interconnects are coupled to the substrate upper terminals. An encapsulant covers portions of the substrate and the vertical interconnects. The vertical interconnects are exposed from an upper side of the encapsulant. A redistribution structure is over the encapsulant and includes a redistribution structure upper side, a redistribution structure lower side, a redistribution dielectric structure, and a redistribution conductive structure. The redistribution structure includes redistribution upper terminals adjacent to the redistribution structure upper side and redistribution bottom terminals adjacent to the redistribution lower side. The redistribution bottom terminals are coupled to the vertical interconnects and the redistribution upper terminals.

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.

Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.

Abstract: Embodiments of methods of die stacking are provided herein. In some embodiments, a method of die stacking with die-to-wafer bonding includes: bonding a plurality of first dies to a substrate via a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor device is picked up from a carrier by a pick and place device, wherein the pick and place device includes a flexible head having a bonding portion configured to be in contact with the semiconductor device, a neck portion connecting the bonding portion, wherein a minimum width of the neck portion is substantially smaller than a maximum width of the bonding portion. The semiconductor device is placed and pressed onto a substrate by the pick and place device. An encapsulating material is formed over the substrate to laterally encapsulating the semiconductor device. A redistribution structure is formed over the semiconductor device and the encapsulating material. The substrate is removed.

Abstract: An antenna package includes a redistribution layer (RDL) structure having a top surface and a bottom surface opposite to the top surface and a TSV die disposed on the top surface of the RDL structure and encapsulated by a molding compound. The TSV die includes an active side and a rear side, and a sidewall of the TSV die is covered with the molding compound. The TSV die includes a plurality of through-silicon-vias including RF signal vias and ground vias penetrating through an entire thickness of the TSV die. An antenna structure is disposed on the rear side of the TSV die and is connected to the RF signal vias and ground vias.

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A magnetic film material is formed over the encapsulant. The magnetic film material may extend down a side surface of the semiconductor device. The magnetic film material is subject to laser spike annealing in a magnetic field. A shielding layer is formed over the magnetic film material. The laser spike annealing of the magnetic film material in the magnetic field can be done after forming the shielding layer. The shielding layer may extend down a side surface of the semiconductor device. A first magnet is disposed on a first side of the semiconductor device. A second magnet is disposed on a second side of the semiconductor device opposite the first side of the semiconductor device.

Abstract: A package structure and methods for forming the package structure are provided. The package structure includes a package component, an encapsulant disposed around the package component, and a redistribution structure disposed over the package component and the encapsulant. The package component includes a substrate, a protection structure, which includes an organic material, over a first surface of the substrate, and a multi-layered structure encapsulated by the protection structure. Sidewalls of the multi-layered structure are spaced apart from the encapsulant by the protection structure.

Abstract: Methods and OLED devices are provided in which organic emissive materials are deposited over a substrate via OVJP print heads in a continuous line extending from one edge of the active display portion of a substrate to another. The print heads are arranged such that the sidewalls of the OVJP jet are disposed over non-emissive insulating portions of the display panel, thereby allowing for improved pixel density and resolution in comparison to conventional OVJP and similar techniques.

Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

Abstract: A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a first surface and a second surface opposite to the first surface; a first electronic component mounted on the first surface of the substrate; a second electronic component mounted on the second surface; and a contact pad formed on the second surface of the substrate, wherein the contact pad is outside of a projection of the second electronic component on the second surface of the substrate; and a first encapsulant disposed on the first surface of the substrate and covering the first electronic component; forming a second encapsulant over and around the second electronic component, wherein the contact pad is exposed from the second encapsulant; planarizing the second encapsulant to expose the second electronic component; and forming a bump on the contact pad of the second surface of the substrate.

Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.

Abstract: A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.

Abstract: A packaging structure comprising a first antenna layer on a protective layer, a dielectric layer, a first plastic packaging layer over the first antenna layer, a second conductive pillar, a chip, a redistribution layer, and a second plastic packaging layer, the first conductive pillar is electrically connected to the first antenna layer, the dielectric layer is formed over the first conductive pillar, the second antenna layer is electrically connected to the first conductive pillar, the second conductive pillar is formed over the dielectric layer and electrically connected to the second antenna layer, the chip layer is formed over the dielectric layer, the redistribution layer is provided with conductive bumps and electrically connected to the chip and the second antenna layer, and the second plastic packaging layer encapsulates the second antenna layer and the chip. Chip and multiple antennas are packaged with one carrier substrate, reducing size.

Abstract: In some examples, a method for manufacturing a semiconductor package comprises coupling first and second semiconductor dies to a metal frame; covering the first and second semiconductor dies and the metal frame with a mold compound; coupling first and second passive components to the first and second semiconductor dies, the first and second passive components on an external surface of the mold compound; sawing through a portion of the metal frame from a first direction to form a first vertical surface of the metal frame, the first vertical surface having a first roughness due to the sawing; and laser cutting through the mold compound and a remainder of the metal frame from a second direction opposing the first direction to form a second vertical surface on the metal frame and a third vertical surface on the mold compound, the second vertical surface having a second roughness due to the laser cutting and the third vertical surface having a third roughness due to the laser cutting.