Patents Examined by Jay C Chang
-
Patent number: 11616065Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.Type: GrantFiled: November 5, 2020Date of Patent: March 28, 2023Inventors: Jiyoung Kim, Kiseok Lee, Bong-Soo Kim, Junsoo Kim, Dongsoo Woo, Kyupil Lee, HyeongSun Hong, Yoosang Hwang
-
Patent number: 11616159Abstract: A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure.Type: GrantFiled: December 23, 2020Date of Patent: March 28, 2023Assignees: SunPower Corporation, Total Marketing ServicesInventors: Matthieu Moors, David D. Smith, Gabriel Harley, Taeseok Kim
-
Patent number: 11616026Abstract: A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.Type: GrantFiled: January 17, 2020Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun Yi Wu, Chen-Hua Yu
-
Patent number: 11613697Abstract: A phosphor may have the empirical formula: (AB)1+x+2yAl11?x?y(AC)xLiyO17:E, where 0<x+y<11; AC=Mg, Ca, Sr, Ba and/or Zn; AB=Na, K, Rb, and/or Cs; and E=Eu, Ce, Yb, and/or Mn. The phosphor may be used in conversion LED components.Type: GrantFiled: September 27, 2018Date of Patent: March 28, 2023Assignee: OSRAM Opto Semiconductors GmbHInventors: Alexey Marchuk, Dominik Baumann
-
Patent number: 11610922Abstract: An array substrate, a display panel, and a method of fabricating an array substrate are provided. The array substrate includes a display region and a non-display region. The array substrate further includes a substrate, a first transparent layer disposed on the substrate corresponding to the display region, an interlayer insulating layer disposed on the substrate, and a second transparent layer disposed on the interlayer insulating layer.Type: GrantFiled: August 29, 2019Date of Patent: March 21, 2023Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Xingyu Zhou
-
Patent number: 11610849Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.Type: GrantFiled: December 1, 2020Date of Patent: March 21, 2023Assignee: STMicroelectronics S.r.l.Inventor: Paolo Crema
-
Patent number: 11605597Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: GrantFiled: April 17, 2020Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
-
Patent number: 11605570Abstract: A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.Type: GrantFiled: September 10, 2020Date of Patent: March 14, 2023Assignee: Rockwell Collins, Inc.Inventors: Richard Korneisel, Nathaniel P. Wyckoff, Brandon C. Hamilton, Bret W. Simon, Jacob R. Mauermann
-
Patent number: 11605763Abstract: A light emitting diode package is disclosed. The light emitting diode package includes a light emitting diode chip emitting light and a light transmissive member. The light transmissive member covers at least an upper surface of the light emitting diode chip and includes a light transmissive resin and reinforcing fillers. The reinforcing fillers have at least two side surfaces having different lengths and are dispersed in the light transmissive resin.Type: GrantFiled: July 30, 2020Date of Patent: March 14, 2023Assignee: SEOUL SEMICONDUCTOR CO., LTD.Inventors: Myung Jin Kim, Kwang Yong Oh
-
Patent number: 11600902Abstract: A semiconductor device includes: a dielectric substrate; an integrated circuit (IC) die disposed inside an opening of the dielectric substrate, where the IC die is configured to transmit or receive radio frequency (RF) signals; a dielectric material in the opening of the dielectric substrate and around the IC die; a redistribution structure along a first side of the dielectric substrate, where a first conductive feature of the redistribution structure is electrically coupled to the IC die; a second conductive feature along a second side of the dielectric substrate opposing the first side; a via extending through the dielectric substrate, where the via electrically couples the first conductive feature and the second conductive feature; and an antenna at the second side of the dielectric substrate, where the second conductive feature is electrically or electromagnetically coupled to the antenna.Type: GrantFiled: February 13, 2020Date of Patent: March 7, 2023Assignee: Infineon Technologies AGInventors: Ashutosh Baheti, EungSan Cho, Saverio Trotta
-
Patent number: 11594425Abstract: A semiconductor package structure, including a lead frame, a die disposed on the front side of the lead frame, and a molding piece disposed on the lead frame and encapsulates the die, wherein the lead frame is provided with two extension portions extending respectively from two sides of the molding piece, and the extension portion is provided with recessed front surface and back surface on which a plating layer is formed.Type: GrantFiled: November 12, 2020Date of Patent: February 28, 2023Assignee: PANJIT INTERNATIONAL INC.Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
-
Patent number: 11586702Abstract: Embodiments described herein are generally related to a method and a system for performing a computation using a hybrid quantum-classical computing system, and, more specifically, to providing an approximate solution to an optimization problem using a hybrid quantum-classical computing system that includes a group of trapped ions. A hybrid quantum-classical computing system that is able to provide a solution to a combinatorial optimization problem may include a classical computer, a system controller, and a quantum processor. The methods and systems described herein include an efficient and noise resilient method for constructing trial states in the quantum processor in solving a problem in a hybrid quantum-classical computing system, which provides improvement over the conventional method for computation in a hybrid quantum-classical computing system.Type: GrantFiled: May 5, 2020Date of Patent: February 21, 2023Assignee: IONQ, INC.Inventors: Omar Shehab, Isaac Hyun Kim
-
Patent number: 11588081Abstract: A semiconductor device package includes a light-emitting device, a diffuser structure, a first optical sensor, and a second optical sensor. The light-emitting device has a light-emitting surface. The diffuser structure is above the light-emitting surface of the light-emitting device. The first optical sensor is disposed below the diffuser structure, and the first optical sensor is configured to detect a first reflected light reflected by the diffuser structure. The second optical sensor is disposed below the diffuser structure, and the second optical sensor is configured to detect a second reflected light reflected by the diffuser structure.Type: GrantFiled: March 4, 2020Date of Patent: February 21, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsin-Ying Ho, Hsun-Wei Chan, Shih-Chieh Tang, Lu-Ming Lai
-
Patent number: 11587840Abstract: Provided is a semiconductor device including: a substrate; an electrode layer provided on the substrate; a semiconductor chip being provided on the electrode layer, including a first side surface portion having a first angle with respect to a substrate surface of the substrate, and including a second side surface portion being provided below the first side surface portion and having a second angle smaller than the first angle with respect to the substrate surface; and a resin being provided around the electrode layer and the semiconductor chip and being in contact with the first side surface portion and the second side surface portion.Type: GrantFiled: September 4, 2020Date of Patent: February 21, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Hideyuki Yamauchi
-
Patent number: 11587800Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device.Type: GrantFiled: May 22, 2020Date of Patent: February 21, 2023Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Khay Chwan Andrew Saw, Chee Voon Tan
-
Patent number: 11588086Abstract: A micro-LED display includes a casing, a light-transmitting cover, a micro-LED array substrate, a circuit board, and at least one functional component. The light-transmitting cover is disposed on the casing and has a display area, a non-display area, and a plurality of first vias. The first vias are located in the display area. The micro-LED array substrate is disposed between the light-transmitting cover and the casing. The micro-LED array substrate has a plurality of second vias overlapped with the first vias in an orthogonal projection direction. The circuit board is disposed between the micro-LED array substrate and the casing, and the circuit board has a functional component disposing area overlapped with the display area in the orthogonal projection direction. The functional component is disposed in the functional component disposing area. The functional component is overlapped with the second vias in the orthogonal projection direction.Type: GrantFiled: November 20, 2020Date of Patent: February 21, 2023Assignee: PlayNitride Display Co., Ltd.Inventors: Kuan-Yung Liao, Yun-Li Li
-
Patent number: 11581273Abstract: A semiconductor device package includes a first circuit layer and an emitting device. The first circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device is disposed on the second surface of the first circuit layer. The emitting device has a first surface facing the second surface of the first circuit layer, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device has a conductive pattern disposed on the second surface of the emitting device. The lateral surface of the emitting device and the lateral surface of the first circuit layer are discontinuous.Type: GrantFiled: December 26, 2019Date of Patent: February 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Meng-Wei Hsieh
-
Patent number: 11574933Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.Type: GrantFiled: July 9, 2021Date of Patent: February 7, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
-
Patent number: 11575073Abstract: A light-emitting device includes: a substrate; a light-emitting element disposed on the substrate; a light-transmissive member disposed on a light extraction surface of the light-emitting element; a cover that covers the light-emitting element with a gap between the cover and the light-emitting element, the cover including: an upper portion that is transmissive to light emitted from the light-emitting element, a sidewall extending along a peripheral edge of the upper portion and having an outer lateral surface, and a recess defined by the upper portion and the sidewall; and a fixing member arranged on at least a part of the outer lateral surface of the sidewall of the cover. The fixing member is formed of a material that is deformable due to a pressing force generated in the event of an engagement with a counterpart member.Type: GrantFiled: September 17, 2020Date of Patent: February 7, 2023Assignee: NICHIA CORPORATIONInventors: Tsuyoshi Okahisa, Tomohito Shinomiya, Daizo Kiba
-
Patent number: 11569422Abstract: A semiconductor package is provided in the present disclosure. The semiconductor package comprises: a substrate, an electronic device disposed on the substrate, a lid disposed on the substrate and surrounding the electronic device an encapsulant formed over the substrate, encapsulating the electronic device and the lid; and a plurality of fillers in the encapsulant, configured to diffuse light interacting with the electronic device. In this way, through the use of the encapsulant including the fillers distributed therein, additional optical filters and diffusers are not needed. Also, through the use of the lid, undesired stray light can be prevented from being interacting with the electronic device.Type: GrantFiled: September 9, 2020Date of Patent: January 31, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Tang Chu, Tsu-Hsiu Wu, Chun Yu Ko