Abstract: An antenna package includes a redistribution layer (RDL) structure having a top surface and a bottom surface opposite to the top surface and a TSV die disposed on the top surface of the RDL structure and encapsulated by a molding compound. The TSV die includes an active side and a rear side, and a sidewall of the TSV die is covered with the molding compound. The TSV die includes a plurality of through-silicon-vias including RF signal vias and ground vias penetrating through an entire thickness of the TSV die. An antenna structure is disposed on the rear side of the TSV die and is connected to the RF signal vias and ground vias.

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A magnetic film material is formed over the encapsulant. The magnetic film material may extend down a side surface of the semiconductor device. The magnetic film material is subject to laser spike annealing in a magnetic field. A shielding layer is formed over the magnetic film material. The laser spike annealing of the magnetic film material in the magnetic field can be done after forming the shielding layer. The shielding layer may extend down a side surface of the semiconductor device. A first magnet is disposed on a first side of the semiconductor device. A second magnet is disposed on a second side of the semiconductor device opposite the first side of the semiconductor device.

Abstract: Methods and OLED devices are provided in which organic emissive materials are deposited over a substrate via OVJP print heads in a continuous line extending from one edge of the active display portion of a substrate to another. The print heads are arranged such that the sidewalls of the OVJP jet are disposed over non-emissive insulating portions of the display panel, thereby allowing for improved pixel density and resolution in comparison to conventional OVJP and similar techniques.

Abstract: A package structure and methods for forming the package structure are provided. The package structure includes a package component, an encapsulant disposed around the package component, and a redistribution structure disposed over the package component and the encapsulant. The package component includes a substrate, a protection structure, which includes an organic material, over a first surface of the substrate, and a multi-layered structure encapsulated by the protection structure. Sidewalls of the multi-layered structure are spaced apart from the encapsulant by the protection structure.

Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

Abstract: A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a first surface and a second surface opposite to the first surface; a first electronic component mounted on the first surface of the substrate; a second electronic component mounted on the second surface; and a contact pad formed on the second surface of the substrate, wherein the contact pad is outside of a projection of the second electronic component on the second surface of the substrate; and a first encapsulant disposed on the first surface of the substrate and covering the first electronic component; forming a second encapsulant over and around the second electronic component, wherein the contact pad is exposed from the second encapsulant; planarizing the second encapsulant to expose the second electronic component; and forming a bump on the contact pad of the second surface of the substrate.

Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.

Abstract: A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.

Abstract: A packaging structure comprising a first antenna layer on a protective layer, a dielectric layer, a first plastic packaging layer over the first antenna layer, a second conductive pillar, a chip, a redistribution layer, and a second plastic packaging layer, the first conductive pillar is electrically connected to the first antenna layer, the dielectric layer is formed over the first conductive pillar, the second antenna layer is electrically connected to the first conductive pillar, the second conductive pillar is formed over the dielectric layer and electrically connected to the second antenna layer, the chip layer is formed over the dielectric layer, the redistribution layer is provided with conductive bumps and electrically connected to the chip and the second antenna layer, and the second plastic packaging layer encapsulates the second antenna layer and the chip. Chip and multiple antennas are packaged with one carrier substrate, reducing size.

Abstract: In some examples, a method for manufacturing a semiconductor package comprises coupling first and second semiconductor dies to a metal frame; covering the first and second semiconductor dies and the metal frame with a mold compound; coupling first and second passive components to the first and second semiconductor dies, the first and second passive components on an external surface of the mold compound; sawing through a portion of the metal frame from a first direction to form a first vertical surface of the metal frame, the first vertical surface having a first roughness due to the sawing; and laser cutting through the mold compound and a remainder of the metal frame from a second direction opposing the first direction to form a second vertical surface on the metal frame and a third vertical surface on the mold compound, the second vertical surface having a second roughness due to the laser cutting and the third vertical surface having a third roughness due to the laser cutting.

Abstract: A method for manufacturing a power device fabrication panel includes aligning a first alignment mark in a lead frame of a power device substrate array with a second alignment mark in a bonding fixture. The power device substrate array includes a plurality of power device pockets, the bonding fixture includes a plurality of power device openings, and the power device openings are in assembly alignment with the power device pockets when the first alignment mark is aligned with the second alignment mark. And with the bonding fixture power device openings in assembly alignment with the power device pockets of the power device substrate array, a plurality of power devices are moved at least partially through the aligned power device openings and into the power device pockets where they are bonded.

Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) measuring an amount of a molding powder; (b) controlling the amount of a molding powder; and (c) dispensing the molding powder on an assembly structure including a carrier and at least one semiconductor device disposed on the carrier.

Abstract: A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.

Abstract: A method for high volume manufacture of highly integrated power electronics embedded printed circuit board (PCB)—cold plate assemblies or units includes assembling an integrated power electronics embedded PCB fabrication panel onto a cold plate fabrication panel and forming an integrated power electronics embedded PCB—cold plate fabrication panel. The integrated power electronics embedded PCB—cold plate fabrication panel is cut into a plurality of highly integrated power electronics embedded PCB—cold plate assemblies such that the plurality of highly integrated power electronics embedded PCB—cold plate assemblies individually include an integrated power electronics embedded PCB attached to and in thermal communication with a cold plate. Also, the cold plate can include a fluid chamber configured for a cooling fluid to flow therethrough.

Abstract: Provided is a semiconductor package including a redistribution structure including first surface and a second surface opposite to each other, the redistribution structure including a redistribution layer, a semiconductor chip on the first surface of the redistribution structure, the semiconductor chip being electrically connected to the redistribution layer, an encapsulant on the semiconductor chip, at least one antenna pattern on the encapsulant, a side wiring line extending along a surface of the encapsulant from one end of the antenna pattern to the redistribution layer, and electronic devices on the second surface of the redistribution structure, the electronic devices being electrically connected to the redistribution layer, wherein the semiconductor chip and the antenna pattern are configured to transmit and receive a signal to and from each other through the electronic devices.

Abstract: In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.

Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.

Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.