Patents Examined by Jay C Chang
  • Patent number: 11955479
    Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yiqi Tang, Rajen Manicon Murugan, Makarand Ramkrishna Kulkarni
  • Patent number: 11955349
    Abstract: A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien Ling Hwang
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Patent number: 11935761
    Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11935821
    Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges (802) of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate (102) to permit electroplating. In addition, the method may be used to directly connect a semiconductor die (202) to the metal substrate (102) of the package.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Nazila Dadvand
  • Patent number: 11930658
    Abstract: A display apparatus includes a substrate including a main display area and a component area. The component area includes an auxiliary display area and a transmission area. Main display elements are disposed in the main display area. Auxiliary display elements are disposed in the component area. A thin-film encapsulation layer covers the main display elements and the auxiliary display elements. An optical functional layer is disposed on the thin-film encapsulation layer and includes a polarization layer. The polarization layer includes a first portion disposed in the transmission area and a second portion disposed in the main display area and the auxiliary display area.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngki Chai, Seonggeun Won, Kwanhee Lee, Youngji Kim, Yiseul Um, Younghoon Lee, Youngseo Choi
  • Patent number: 11929261
    Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11929326
    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11929452
    Abstract: A method for manufacturing a light-emitting device includes: forming a cover, which comprises: sandwiching a fixing member by a molding device, injecting a light-transmissive material into a space defined in the molding device, and hardening or curing the injected light-transmissive material, wherein the formed cover comprises an upper portion, a sidewall, and a recess, the cover being integrated with the fixing member such that the fixing member projects from a part of an outer lateral surface of the sidewall; disposing a light-transmissive member on a light extraction surface of a light-emitting element to be disposed on a substrate; and disposing the cover so that the light-emitting element is housed in the recess. The fixing member is formed of a material that is deformable due to a pressing force generated in the event of an engagement with a counterpart member.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 12, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Tsuyoshi Okahisa, Tomohito Shinomiya, Daizo Kiba
  • Patent number: 11923320
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
  • Patent number: 11923308
    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun
  • Patent number: 11923654
    Abstract: Described herein are one or more methods for integrating an optical component into an integrated photonics device. The die including a light source, an outcoupler, or both, may be bonded to a wafer having a cavity. The die can be encapsulated using an insulating material, such as an overmold, that surrounds its edges. Another (or the same) insulating material can surround conductive posts. Portions of the die, the overmold, and optionally, the conductive posts can be removed using a grinding and polishing process to create a planar top surface. The planar top surface enables flip-chip bonding and an improved connection to a heat sink. The process can continue with forming one or more additional conductive layers and/or insulating layers and electrically connecting the p-side and n-side contacts of the laser to a source.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Apple Inc.
    Inventors: Michael J. Bishop, Jason Pelc, Vijay M. Iyer, Alex Goldis
  • Patent number: 11916025
    Abstract: A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Tzuan-Horng Liu, Chia-Hung Liu, Hao-Yi Tsai
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11910610
    Abstract: A semiconductor device includes a substrate, a gate insulating layer on the substrate, and a stacked semiconductor layer. The stacked semiconductor layer includes a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor, a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor. The semiconductor device further includes a metal layer on or above the stacked semiconductor layer. The third layer includes less phosphorus than the first layer or does not include phosphorus.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Tatsuya Hosoda, Yasuhisa Naruta
  • Patent number: 11903300
    Abstract: Methods and OLED devices are provided in which organic emissive materials are deposited over a substrate via OVJP print heads in a continuous line extending from one edge of the active display portion of a substrate to another. The print heads are arranged such that the sidewalls of the OVJP jet are disposed over non-emissive insulating portions of the display panel, thereby allowing for improved pixel density and resolution in comparison to conventional OVJP and similar techniques.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: February 13, 2024
    Assignee: Universal Display Corporation
    Inventors: JinJu Lin, Gregg Kottas, William E. Quinn
  • Patent number: 11901360
    Abstract: In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: February 13, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Patent number: 11901266
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li Yang, Wen-Hsiung Lu, Lung-Kai Mao, Fu-Wei Liu, Mirng-Ji Lii
  • Patent number: 11894438
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
  • Patent number: 11888099
    Abstract: A light emitting diode (LED) package structure include an electrically-insulated frame, a trough, a LED chip, a fluorescent colloid and at least two spacing members. The electrically-insulated frame has a surface with four corners. The trough is recessed in the surface. The LED chip is located in the trough. The fluorescent colloid is filled within the trough to cover the LED chip. The spacing members protrude from two of the four corners on the surface, wherein a glue escape gap is defined between each spacing member and a boundary of the trough.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 30, 2024
    Assignee: Lextar Electronics Corporation
    Inventor: Chien-Hsin Tu