Patents Examined by Jay C Chang
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Patent number: 12046526Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: GrantFiled: May 3, 2022Date of Patent: July 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 12040350Abstract: The display device includes a first substrate, a second substrate, a red filter layer, a green filter layer, a blue filter layer, a first light emitting diode and a second light emitting diode. The red filter layer, the green filter layer and the blue filter layer are disposed between the first substrate and the second substrate. A portion of the red filter layer, a portion of the green filter layer and a portion of the blue filter layer are stacked with each other to form a light blocking structure. The first light emitting diode and the second light emitting diode are disposed between the first substrate and the second substrate and adjacent to each other. An orthographic projection of the light blocking structure on the second substrate is located between orthographic projections of the first light emitting diode and the second light emitting diode on the second substrate.Type: GrantFiled: December 2, 2022Date of Patent: July 16, 2024Assignee: Innolux CorporationInventors: Yi-An Chen, Wan-Ling Huang, Tsau-Hua Hsieh
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Patent number: 12033909Abstract: A die package is provided. The die package may include a laminated carrier including at least one recess, a first die having a frontside, a backside, a frontside metallization on the frontside and a backside metallization on the backside, wherein the first die is arranged in the at least one recess, a first encapsulating material partially encapsulating the first die, by covering at least the frontside metallization or the backside metallization, and an adhesion promoter material between the metallization covered by the first encapsulation material and the first encapsulation material and in direct physical contact with the first encapsulation material and the metallization covered by the first encapsulation material.Type: GrantFiled: June 23, 2020Date of Patent: July 9, 2024Assignee: Infineon Technologies AGInventors: Petteri Palm, Angela Kessler
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Patent number: 12035560Abstract: The present disclosure relates to an organic light-emitting diode. The organic light-emitting diode includes a substrate, an anode layer, an organic functional layer, a cathode layer, and a cover layer that are sequentially stacked from bottom to top.Type: GrantFiled: June 2, 2020Date of Patent: July 9, 2024Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangzhou Chinaray Optoelectronic Materials Ltd.Inventors: Xu Wang, Yue Zhang, Xianjie Li, Munjae Lee, Junyou Pan, Tao Li, Jiahui Tan, Xi Yang
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Patent number: 12033907Abstract: A semiconductor encapsulation material is used to fabricate a semiconductor device. The semiconductor device includes a semiconductor chip and an encapsulating portion. The encapsulating portion is made of a cured product of the semiconductor encapsulation material. The encapsulating portion encapsulates the semiconductor chip. A stress index (SI), given by the following Formula (1), of the semiconductor encapsulation material is equal to or more than 8500. If a volume of the semiconductor chip is represented by Vc and a total volume of the semiconductor chip and the encapsulating portion is represented by Va, the volume Vc and the total volume Va satisfy the following Formula (2). In Formula (1), E? (T) represents a storage modulus, CTE (T) represents a coefficient of thermal expansion, and Mold temp. represents a molding temperature. SI = ? 35 ? ° ? C . Mold ? temp . [ E ? ( T ) × CTE ? ( T ) ] ? dT ( 1 ) Vc Va ? 0.3 .Type: GrantFiled: February 7, 2020Date of Patent: July 9, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Chika Arayama
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Patent number: 12027653Abstract: The invention relates to an illuminating device (1) comprising a substrate (2), a non-transparent spacer (4) which is connected to the substrate (2) so as to be hermetically sealed, an opening in the spacer (4), opposite said substrate (2), and an illumination element (3) positioned beneath the spacer (4) and beneath the opening, which element is connected to the substrate (2) so as to be hermetically sealed, characterized in that the opening in the spacer (4) is closed, so as to be hermetically sealed, by an optical element (5) consisting of a glass material the volume of which comprises at least one luminophore and thus constitutes a luminescent composite glass material.Type: GrantFiled: May 24, 2018Date of Patent: July 2, 2024Assignees: Tridonic Jennersdorf GmbH, W&H Dentalwerk Bürmoos GmbHInventors: Steffen Riemer, Franz Schrank, Patrick Uitz, Wilhelm Brugger, Thomas Irran
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Patent number: 12018375Abstract: There is provided a film forming method of forming a carbon-containing film by a microwave plasma from a microwave source, the film forming method including: a dummy step of performing a dummy process by generating plasma of a first carbon-containing gas within a processing container; a placement step of placing a substrate on a stage within the processing container; and a film forming step of forming the carbon-containing film on the substrate using plasma of a second carbon-containing gas.Type: GrantFiled: November 30, 2020Date of Patent: June 25, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Ryota Ifuku, Takashi Matsumoto, Masahito Sugiura, Makoto Wada
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Patent number: 12022725Abstract: An electronic device with high outcoupling efficiency or a high light-trapping effect is provided. The electronic device includes a first layer and a second layer between a first electrode and a second electrode, the first layer is included between the first electrode and the second layer, the first layer includes a first organic compound and a first substance, the refractive index of a thin film of the first organic compound is higher than or equal to 1 and lower than or equal to 1.75, the first substance has an electron-accepting property, and the second layer has a function of emitting or absorbing light.Type: GrantFiled: February 11, 2021Date of Patent: June 25, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeyoshi Watabe, Satoshi Seo
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Patent number: 12016162Abstract: An electric power converter device includes a first power semiconductor module and a frame for a closed cooler. The first power semiconductor module includes a first base plate having a first main side, a second main side opposite the first main side and a lateral side surface extending along a circumferential edge of the first base plate and connecting the first and the second main side. The frame is attached to the second main side of the first base plate. The first base plate has a first step on the second main side along the circumferential edge of the first base plate to form a first recess along the circumferential edge of the first base plate, in which first recess a first portion of the frame is received.Type: GrantFiled: February 25, 2020Date of Patent: June 18, 2024Assignees: AUDI AG, Hitachi Energy Switzerland AGInventors: Thomas Gradinger, Jürgen Schuderer, Felix Traub, Chunlei Lui, Fabian Mohn, Daniele Torresin
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Patent number: 12009313Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.Type: GrantFiled: October 1, 2021Date of Patent: June 11, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Meng-Jen Wang, Chien-Yuan Tseng, Hung Chen Kuo, Ying-Hao Wei, Chia-Feng Hsu, Yuan-Long Chiao
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Patent number: 12009465Abstract: In a flip-chip LED assembly having an array of LEDs formed on the same substrate, different LEDs of the array have different distances to the n-contacts of the assembly. This may cause current crowding as current has to spread from the n-contacts through the substrate to each the farthest LEDs of the LED array, requiring LEDs that are farther away to be driven with a higher voltage in order to receive a desired amount of current. To spread current more evenly through the LED assembly and reduce a voltage difference between the closest and farthest LEDs of the array, a current spreading layer having a conductive material (e.g., a conductive oxide) is formed on a surface of the substrate of the LED assembly. The current spreading layer may be a bulk layer or be patterned to increase light extraction from the LEDs of the array.Type: GrantFiled: February 25, 2022Date of Patent: June 11, 2024Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Christophe Antoine Hurni, John Michael Goward, Chloe Astrid Marie Fabien
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Patent number: 12010892Abstract: The present disclosure provides a display panel and a manufacturing method thereof. The display panel includes a thin-film transistor structure layer, an OLED light-emitting layer disposed on the thin-film transistor structure layer and including light-emitting color sub-pixels arranged at intervals, a touch layer disposed on the OLED light-emitting layer, and a color filter including color film layers disposed on the light-emitting color sub-pixels and a color resist layer located among the color film layers.Type: GrantFiled: December 30, 2019Date of Patent: June 11, 2024Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Lei Wang
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Patent number: 12010847Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.Type: GrantFiled: March 10, 2022Date of Patent: June 11, 2024Assignee: Micron Technology, Inc.Inventors: Darwin A. Clampitt, Matthew J. King, John D. Hopkins, M. Jared Barclay
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Patent number: 12002909Abstract: A light emitting device includes a package for surface mounting including a plurality of leads, three leads of the plurality of leads respectively including an exposed region exposed from the dark-colored resin at a primary surface of the package, with first to third recesses each defined in the exposed region of a respective one of the three leads; first to third light emitting elements configured to emit first to third light, respectively; and a mold resin including first to third lens portions overlapping with the first to third recesses and the first to third light emitting elements, respectively, in a plan view, and colored in a similar color as the first to third light, respectively.Type: GrantFiled: August 24, 2021Date of Patent: June 4, 2024Assignee: NICHIA CORPORATIONInventor: Kenta Mitsuyama
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Patent number: 11996446Abstract: Compositions and methods related to straining defect doped materials as well as their methods of use in electrical circuits are generally described.Type: GrantFiled: August 11, 2021Date of Patent: May 28, 2024Assignees: Massachusetts Institute of Technology, Nanyang Technological UniversityInventors: Ming Dao, Ju Li, Zhe Shi, Subra Suresh
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Patent number: 11990367Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.Type: GrantFiled: August 12, 2021Date of Patent: May 21, 2024Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
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Patent number: 11990520Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.Type: GrantFiled: November 22, 2021Date of Patent: May 21, 2024Assignee: INFINEON TECHNOLOGIES AGInventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
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Patent number: 11990573Abstract: A light emitting device including a fluorescent material with reduced hue, and a method of manufacturing the light emitting device are provided. A light emitting device 100 includes: a light emitting element 1; a first light-transmissive member 3 covering the light emitting element 1; and a light diffusing member 5 contained in the first light-transmissive member 3. The light diffusing member 5 includes hollow particles. The surface of the first light-transmissive member 3 has irregular shapes attributed to the light diffusing member 5. The first light-transmissive member 3 is covered with a second light-transmissive member 4. The second light-transmissive member 4 has a convex structure in which the center is the uppermost point. The irregular shapes attributed to the light diffusing member 5 are covered with the second light-transmissive member 4.Type: GrantFiled: April 29, 2022Date of Patent: May 21, 2024Assignee: NICHIA CORPORATIONInventors: Shoichi Kashihara, Masanobu Sato
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Patent number: 11984359Abstract: A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.Type: GrantFiled: February 28, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Pokuan Ho, Hsin-Ping Chen, Chia-Tien Wu
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Patent number: 11984533Abstract: A light emitting device according to an embodiment of the present disclosure includes: a first layer including Alx2Inx1Ga(1-x1-x2) N (0<x1<1, 0?x2<1); a second layer that is provided on the first layer and includes Aly2Iny1Ga(1-y1-y2) N (0<y1<1, 0?y2<1) that is lattice relaxed with respect to the first layer; and a third layer that is provided on the second layer, includes Alz2Inz1Ga(1-z1-z2) N (0<z1<1, 0?z2<1) that is lattice relaxed with respect to the second layer, and includes an active layer. A lattice constant aGAN of GaN in an in-plane direction, a lattice constant al of the first layer in an in-plane direction, a lattice constant a2 of the second layer in an in-plane direction, and a lattice constant a3 of the third layer in an in-plane direction have a relationship of aGAN<a2<a1, a3.Type: GrantFiled: July 1, 2019Date of Patent: May 14, 2024Assignee: Sony CorporationInventors: Kunihiko Tasai, Hiroshi Nakajima, Hidekazu Kawanishi, Katsunori Yanashima