Abstract: A semiconductor device includes a conductive pattern, and a capacitor electrically connected to the conductive pattern. The capacitor includes a first electrode structure electrically connected to the conductive pattern, a dielectric layer disposed on the first electrode structure, a second electrode structure disposed on the dielectric layer, and a plate electrode disposed on the second electrode structure. The second electrode structure includes a first electrode material layer including a first metal element and a nitrogen element, and a first protective material layer including a second metal element, a Group 14 element, and an oxygen element.

Abstract: A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, an epoxy seal is created on four walls of a lid enclosing the cavity. A further sputtered metal layer is added over the epoxy seal to provide additional structural rigidity, electromagnetic emission suppression and to assist in preventing leaks through the epoxy seal.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A method for forming a die package structure, including disposing a plurality of dies on a carrier substrate, wherein the top surface of each die has a plurality of signal junctions. The method also includes forming a vertical wire on each of the signal junctions, forming a supporting dielectric layer on the carrier substrate, wherein the supporting dielectric layer covers the dies and exposes the top of the vertical wires, and forming a plurality of redistribution traces on the supporting dielectric layer, wherein the redistribution traces are electrically connected to each of the vertical wires. The method further includes forming a bump at the bonding site of each of the redistribution traces, and performing a cutting process to singulate the dies.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure and a light-emitting structure. The first semiconductor structure includes a first confinement layer and a first cladding layer adjacent to the first confinement layer. The second semiconductor structure is located on the first semiconductor structure and includes a second confinement layer. The light-emitting structure is located between the first semiconductor structure and the second semiconductor structure. The light-emitting structure includes a first multiple quantum well structure containing a plurality of semiconductor stacks. Each of the semiconductor stacks is stacked by a well layer and a barrier layer. The first confinement layer and the second confinement layer are adjacent to the light emitting structure. The well layer and the barrier layer in each of the semiconductor stacks include the same quaternary semiconductor material including InGaAsP, AlGaInAs or InGaNAs.

Abstract: A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure connected to the circuit elements, and a peripheral region insulating layer covering the circuit elements; and a second semiconductor structure including a second substrate on the first substrate, a first stack structure including first and second gate electrodes spaced apart from each other and stacked on the second substrate, interlayer insulating layers alternately stacked with the first and second gate electrodes, first and second contact plugs passing through the first and second gate electrodes, and contact plug insulating layers alternately disposed with the interlayer insulating layers and surrounding the contact plugs.

Abstract: An electronic circuit package disclosed in the present disclosure includes: a package board having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface connecting the upper and bottom surfaces; an electronic component mounted on the upper surface of the package board; a first protective layer covering the upper surface of the package board so as to embed therein the electronic component; and a second protective layer covering the side surface of the package board. The first and second protective layers contact each other.

Abstract: A method of manufacturing an interposer product that includes: forming on a same side of an interposer substrate, by a common process, first and second portions of a gold layer, wherein the first portion of the gold layer constitutes a wire-bonding pad; depositing a Au—Sn solder on the second portion of the gold layer, the Au—Sn solder comprising a gold-tin alloy having a first composition; merging the deposited Au—Sn solder with the second portion of the gold layer by performing a reflow process to form at least one bonding bump, wherein a majority of the bonding bump is made of a eutectic composition of the gold-tin alloy, and wherein the first composition has a smaller proportion of gold than is in the eutectic composition of the gold-tin alloy; and planarizing the bonding bump to form a flat bonding bump having a selected height.

Abstract: An electronic package is provided, in which an electronic component and conductors are disposed on a substrate structure, and the electronic component and the conductors are covered by an encapsulation layer. A conductive layer is formed on side surfaces of the encapsulation layer and in contact with the conductors, where the conductors are bonding wires used in a wire bonding process. Therefore, a conventional heat sink is replaced by the conductors, thereby reducing a use area of the substrate structure.

Abstract: A method of forming a semiconductor structure is provided, which includes forming via structures over a first carrier wafer. A unit via assembly structure is repeated in two directions over the first carrier wafer. Each instance of the unit via assembly is formed within a respective unit area of repetition. Each instance of the unit via assembly includes through integrated-fan-out via (TIV) structures and two alignment mark via assemblies located in two corner regions of a respective unit area and are diagonally spaced apart from each other. Corner locations of the unit areas of repetition may be identified using the alignment mark via assemblies within unit areas of repetition. At least one local silicon interconnect (LSI) bridge may be placed within each unit area of repetition using a pick and place tool.

Abstract: There is provided a method for manufacturing a wiring substrate in which damage to a device layer during carrier release can be suppressed, and a photolithography process can be carried out with good accuracy on the device layer after carrier release. This method includes: providing a laminated sheet including a carrier, a release layer, a metal layer, and a device layer in order; making a cut line from a surface of the laminated sheet on the carrier side so that the cut line passes through the carrier, the release layer, and the metal layer when the laminated sheet is seen in a cross-sectional view; and removing outer edge portions outside the cut line in the carrier, the release layer, and the metal layer, thereby exposing part of a surface of the device layer on the metal layer side to form a pressurizable exposed portion for promoting release of the carrier.

Abstract: A semiconductor device has a substrate and encapsulant deposited over the substrate. An electrical connector is disposed over the substrate outside the encapsulant. An antenna can be formed over the substrate. A first shielding material is disposed over a portion of the encapsulant without covering the electrical connector with the first shielding material. The first shielding material is disposed over the portion of the encapsulant and the portion of the substrate using a direct jet printer. A light source emitting an ultraviolet light or intense pulsed light is directed at the first shielding material to induce sintering. A cover is disposed over the electrical connector. A second shielding material is disposed over the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps the first shielding material and covers a side surface of the encapsulant and a side surface of the substrate.

Abstract: A method for manufacturing a power transistor. The method includes: applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate, producing an expansion layer, which is situated inside the first epitaxial layer, producing various implanted areas starting from the front side of the semiconductor substrate, producing a trench structure starting from the front side of the semiconductor substrate, producing first isolation areas in the surroundings of the trench structure, producing transistor heads, and applying metal layers.

Abstract: A fan-out wafer-level packaging structure and a method for manufacturing it are disclosed. The structure includes: a rewiring layer, a chip, an electrical component, a protective layer made of UV-curable adhesive, a molding layer, and a solder ball. The protective layer is disposed on surfaces of the electrical component, sealing the electrical component, and ensuring its safe operation and reliability, mitigating risks of melting and spillage of solder in the electrical component, and preventing electrical shorts and delamination between molding layers and the electrical component. The protective layer is formed by UV-curing or UV/thermal-dual-curing, to prevent loss of upper portions of the adhesive resulted from the upper portions flowing downward after dispensing. A dual-curing process can further solidify the protective layer, enabling the protective layer to better seal and protect the electrical component.

Abstract: In one example, an electronic device includes a substrate including a substrate upper side and a conductive structure comprising substrate upper terminals adjacent to the substrate upper side. Vertical interconnects are coupled to the substrate upper terminals. An encapsulant covers portions of the substrate and the vertical interconnects. The vertical interconnects are exposed from an upper side of the encapsulant. A redistribution structure is over the encapsulant and includes a redistribution structure upper side, a redistribution structure lower side, a redistribution dielectric structure, and a redistribution conductive structure. The redistribution structure includes redistribution upper terminals adjacent to the redistribution structure upper side and redistribution bottom terminals adjacent to the redistribution lower side. The redistribution bottom terminals are coupled to the vertical interconnects and the redistribution upper terminals.

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.

Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.

Abstract: Embodiments of methods of die stacking are provided herein. In some embodiments, a method of die stacking with die-to-wafer bonding includes: bonding a plurality of first dies to a substrate via a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor device is picked up from a carrier by a pick and place device, wherein the pick and place device includes a flexible head having a bonding portion configured to be in contact with the semiconductor device, a neck portion connecting the bonding portion, wherein a minimum width of the neck portion is substantially smaller than a maximum width of the bonding portion. The semiconductor device is placed and pressed onto a substrate by the pick and place device. An encapsulating material is formed over the substrate to laterally encapsulating the semiconductor device. A redistribution structure is formed over the semiconductor device and the encapsulating material. The substrate is removed.

Abstract: An antenna package includes a redistribution layer (RDL) structure having a top surface and a bottom surface opposite to the top surface and a TSV die disposed on the top surface of the RDL structure and encapsulated by a molding compound. The TSV die includes an active side and a rear side, and a sidewall of the TSV die is covered with the molding compound. The TSV die includes a plurality of through-silicon-vias including RF signal vias and ground vias penetrating through an entire thickness of the TSV die. An antenna structure is disposed on the rear side of the TSV die and is connected to the RF signal vias and ground vias.