Abstract: A display device includes a first electrode disposed on a substrate; a light emitting element disposed on the first electrode, the light emitting element being electrically connected to the first electrode; a second electrode disposed on the light emitting element, the second electrode being electrically connected to the light emitting element; a meta structure disposed on the second electrode, the meta structure overlapping the light emitting element; and a bank pattern disposed on the substrate, the bank pattern being spaced apart from the light emitting element.

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

Abstract: A display panel, a method for manufacturing the same, and a display terminal are provided. The display panel includes an array substrate, a light-emitting device layer, and a color resist layer. The light-emitting device layer is disposed on the array substrate and includes a red light-emitting device, a first blue light-emitting device, and a second blue light-emitting device. The color resist layer is disposed on the light-emitting device layer and includes a red color resist, a blue color resist, and a green color conversion unit. The red color resist is disposed corresponding to the red light-emitting device. The blue color resist is disposed corresponding to the first blue light-emitting device. The green color conversion unit is disposed corresponding to the second blue light-emitting device and is configured to convert a light emitted by the second blue light-emitting device into a green light.

Abstract: An ejector pin sliding on membrane-based device and method for mass transfer of mini light-emitting diodes (Mini-LEDs) are provided. The device includes a gantry transverse beam. The gantry transverse beam is provided with an ejector pin base, and the ejector pin base is configured to move along the gantry transverse beam. The ejector pin base is fixedly provided with a vision camera and an ejector pin. A blue membrane is horizontally provided at a side of the gantry transverse beam close to the ejector pin, and is spaced from the gantry beam. A surface of a side of the blue membrane away from the gantry transverse beam is adhesively provided with a plurality of Mini-LED chips arranged evenly. A transfer substrate is horizontally provided at a side of the blue membrane close to the plurality of Mini-LED chips, and is spaced from the blue membrane.

Abstract: A display device and a method for manufacturing same are provided. A display device comprises: a first electrode; a second electrode arranged to be spaced apart from and face the first electrode; a first insulation pattern having at least partial region arranged to overlap the first electrode and having a first side surface spaced apart from a first end portion of the first electrode; a second insulation pattern having at least a partial region arranged to overlap the second electrode and having a second side surface spaced apart from a second end portion of the second electrode facing the first end portion, the second side surface facing the first side surface; at least one uneven pattern provided on the first insulation pattern and the second insulation pattern; and at least one light-emitting element provided between the first insulation pattern and the second insulation pattern and having opposite end portions that are electrically connected to the first electrode and the second electrode, respectively.

Abstract: A light emitting diode (LED) package structure include an electrically-insulated frame, a trough, a LED chip, a fluorescent colloid and at least two spacing members. The electrically-insulated frame has a surface with four corners. The trough is recessed in the surface. The LED chip is located in the trough. The fluorescent colloid is filled within the trough to cover the LED chip. The spacing members protrude from two of the four corners on the surface, wherein a glue escape gap is defined between each spacing member and a boundary of the trough.

Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.

Abstract: The semiconductor device includes a first semiconductor component including a first circuit section and an interconnection connected to the first circuit section, and a second semiconductor component including a second circuit section and a third circuit section and stacked on the first semiconductor component. The interconnection is electrically connected to a first connecting portion and a second connecting portion of a plurality of connecting portions for electrically connecting the first semiconductor component and the second semiconductor component. The second circuit section is electrically connected to the interconnection via the first connecting portion. The third circuit section is electrically connected to the interconnection via the second connecting portion.

Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.

Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.

Abstract: A semiconductor device having a large storage capacity per unit area is provided.

Abstract: An electronic element mounting substrate according to an aspect of the present disclosure is provided with a substrate and a plurality of electrodes. The substrate includes an electronic element mounting region. The plurality of electrodes are located around the electronic element mounting region. The substrate includes the electronic element mounting region and at least one of a first protrusion portion spanning between the plurality of electrodes or a second protrusion portion spanning between the plurality of electrodes from an outer edge of the substrate in a plan view.

Abstract: A carrier film for performing a semiconductor package process on a mother substrate including a multi-layer circuit, a mother substrate, and a method of manufacturing a semiconductor package, the carrier film including a base material layer having a predetermined stiffness; and an adhesive layer configured to attach the base material layer onto the mother substrate, the adhesive layer including a water soluble material, wherein the carrier film includes a plurality of openings passing therethrough from a top surface to a bottom surface thereof.

Abstract: Provided herein are methods of depositing tungsten (W) films without depositing a nucleation layer. In certain embodiments, the methods involve depositing a conformal reducing agent layer of boron (B) and/or silicon (Si) on a substrate. The substrate generally includes a feature to be filled with tungsten with the reducing agent layer conformal to the topography of the substrate including the feature. The reducing agent layer is then exposed to a fluorine-containing tungsten precursor, which is reduced by the reducing agent layer to form a layer of elemental tungsten. The conformal reducing agent layer is converted to a conformal tungsten layer.

Abstract: Color conversion layers, methods of making color conversion layers, monolithic color, micro-light-emitting diode displays and methods of making monolithic, color, micro-light-emitting diode displays are disclosed.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: Methods and apparatus for estimating the fidelity of quantum hardware. In one aspect, a method includes accessing a set of quantum gates; sampling a subset of quantum gates from the set of quantum gates, wherein the subset of quantum gates defines a quantum circuit; applying the quantum circuit to a quantum system and performing measurements on the quantum system to determine output information of the quantum system; calculating output information of the quantum system based on application of the quantum circuit to the quantum system; and estimating a fidelity of the quantum circuit based on the determined output information and the calculated output information of the quantum system.