Patents Examined by Jay C Chang
  • Patent number: 10727143
    Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
  • Patent number: 10727362
    Abstract: In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 28, 2020
    Assignee: First Solar, Inc.
    Inventor: Markus Eberhard Beck
  • Patent number: 10720359
    Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Tobias Herzig
  • Patent number: 10714583
    Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 14, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara, Julien Delalleau
  • Patent number: 10707284
    Abstract: The present disclosure provides an organic light-emitting display panel and a manufacturing method thereof. The organic light-emitting display panel may include: a first anode layer including a number of first anodes; a pixel definition layer defining a number of pixel regions, wherein one of a first opening and a second opening is defined in each of the pixel regions, the second opening has a depth smaller than that of first opening, an inclination angle is formed between the side wall and the bottom surface, and the inclination angle is larger than 90° and smaller than 180°; a second anode layer arranged in second opening; an organic light-emitting layer arranged in the first opening and the second opening. Accordingly, the resolution of the organic light-emitting display panel is improved.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 7, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Linhong Lv
  • Patent number: 10699999
    Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung Jen, Chia-Lun Hsu
  • Patent number: 10700153
    Abstract: A display device including a light-emitting unit is provided. The display device further includes a substrate, a semiconductor layer, and a first sub-pixel unit. The semiconductor layer and the first sub-pixel unit are disposed on the substrate. The first sub-pixel unit includes a storage capacitor. The storage capacitor includes a first electrode and at least part of the semiconductor layer overlapped with the first electrode. In a top view of the display device, an area of the first electrode is greater than an area of the at least part of the semiconductor layer.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 30, 2020
    Inventors: Yang-Chen Chen, Yu-Hsien Wu
  • Patent number: 10699996
    Abstract: A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole of the core member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering at least portions of the core member and the semiconductor chip and filling at least portions of the through-hole; and a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The core member has a recess portion penetrating through at least portions of the core member, and at least a portion of the recess portion is filled with the encapsulant.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bong Soo Kim
  • Patent number: 10700210
    Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 30, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
  • Patent number: 10700264
    Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Chih-Wei Lu, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 10692774
    Abstract: This semiconductor device comprises: an n-type semiconductor substrate which is connected to an output terminal; a first p-type well which is formed in the n-type semiconductor substrate; a first n-type semiconductor region which is formed in the first p-type well and is connected to a control terminal; and a potential separation part which is connected between the first p-type well and a ground terminal. The potential separation part sets the first p-type well and the ground terminal to a same potential when the output terminal is held at a higher potential than the ground terminal, and sets the first p-type well and the output terminal to a same potential when the output terminal is held at a lower potential than the ground terminal.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 23, 2020
    Assignee: Rohm Co., Ltd.
    Inventors: Hirofumi Yuki, Shuntaro Takahashi, Hiroshi Furutani
  • Patent number: 10692779
    Abstract: A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 23, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10685912
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10680201
    Abstract: A display apparatus includes: a substrate; a display unit disposed on the substrate; a barrier unit disposed between the substrate and the display unit; and a buffer unit disposed between the barrier unit and the display unit, wherein a sum of a thickness of the barrier unit and a thickness of the buffer unit is in the range from 0.9 ?m to 3 ?m.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keun-Soo Lee, Yong-Hwan Park, Chi-Wook An, Seong-Jun Lee
  • Patent number: 10679911
    Abstract: Described herein are ILED displays including redundancy in micro-light emitting diode (micro-LED) dies and methods of manufacturing the ILED displays. A micro-LED die emits light of a particular wavelength. The redundancy is added during manufacturing if defective micro-LED dies are identified. Additional micro-LED dies are included in inoperable sub-pixel assemblies to repair the inoperable sub-pixel assemblies that are identified to include defective micro-LED dies. An ILED display therefore includes at least one repaired sub-pixel assembly that includes two defective micro-LED dies and an operable micro-LED die that are coupled to separate branches of a current path from a current source.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 9, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Ilias Pappas, Sean Lord, Yu-Hsuan Li
  • Patent number: 10679914
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 9, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Patent number: 10672651
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Jyu-Horng Shieh
  • Patent number: 10672854
    Abstract: A display device production method for producing a display device including a light emitting element in an active region and a terminal in a non-active region. The display device production method includes arranging a first mask overlapping with an electrode region of the light emitting element and a second mask overlapping with the terminal, on a conductive film that is arranged in the active region and the non-active region and that covers the terminal, and etching the conductive film.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 2, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hiroki Taniyama, Ryosuke Gunji, Shinsuke Saida, Hiroharu Jinmura, Yoshihiro Nakada, Akira Inoue
  • Patent number: 10672686
    Abstract: A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum
  • Patent number: 10672845
    Abstract: A display device according to an embodiment of the present invention includes: an underlying structure layer; a first lower electrode that is arranged on the underlying structure layer; multiple lower electrodes including a second lower electrode adjacent to the first lower electrode; an organic layer that is arranged on the multiple lower electrodes; an upper electrode that is arranged on the organic layer; a first through hole that is arranged between the first lower electrode and the second lower electrode and includes a first inorganic layer at least in a part of an inner face; and a second inorganic layer that is arranged on the upper electrode and is in contact with the first inorganic layer in the inner face of the first through hole.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 2, 2020
    Assignee: Japan Display Inc.
    Inventors: Koji Yasukawa, Hajime Akimoto