Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Abstract: A chip package includes a chip configured to generate and/or receive a signal; a laminate substrate including a substrate integrated waveguide (SIW) for carrying the signal, the substrate integrated waveguide including a chip-to-SIW transition structure configured to couple the signal between the SIW and the chip and a SIW-to-waveguide transition structure configured to couple the signal out of the SIW or into the SIW, wherein the SIW-to-waveguide transition structure includes a waveguide aperture; and a plurality of electrical interfaces arranged about a periphery of the waveguide aperture, the plurality of electrical interfaces configured to receive the signal from the SIW-to-waveguide transition structure and output the signal from the chip package or to couple the signal to the SIW-to-waveguide transition structure and into the chip package.

Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.

Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.

Abstract: A light emitting device includes a substrate, a plurality of first light emitting elements mounted on the substrate, including first LED dies, and emitting light having a first wavelength, and a light guide layer arranged so as to cover the plurality of first light emitting elements, and guiding the light from the plurality of first light emitting elements, wherein when LG1 is a distance between the first LED dies, and ?c is a critical angle of the light emitted from the light guide layer to the air, and a thickness T between the upper surfaces of the first light emitting elements and the upper surface of the light guide layer is equal to or longer than T1 indicated by T1=LG1/(2tan ?c).

Abstract: In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.

Abstract: In this present invention lateral voltage variable capacitor designs are disclosed. The lateral voltage variable capacitor utilizes a dielectric material with an electric field dependent dielectric permittivity (dielectric constant). Variable capacitor structures are defined laterally in the plane of the substrate as opposed to vertical device structures defined out of the plane of the substrate.

Abstract: A micro semiconductor structure includes a substrate, a dissociative layer, a protective layer and a micro semiconductor. The dissociative layer is located on one side of the substrate. The protective layer is located on at least one side of the substrate. The micro semiconductor is located on the side of the substrate. The transmittance of the protective layer for a light source with wavelength smaller than 360 nm is less than 20%.

Abstract: An encapsulation structure, an electronic apparatus, and an encapsulation method are provided. The encapsulation structure includes: a base substrate, an organic encapsulation layer and a barrier dam that are on the base substrate. The barrier dam is disposed outside the organic encapsulation layer; and the barrier dam includes an upper surface away from the base substrate and a side surface facing the organic encapsulation layer, and at least one of the upper surface and the side surface includes a groove and a protrusion.

Abstract: A method for manufacturing a semiconductor device is provided. The manufacturing method includes attaching a substrate to a sheet. The manufacturing method includes fragmenting the substrate into a plurality of individual chips. The manufacturing method includes expanding the sheet to widen the spacing between the plurality of chips. The manufacturing method includes covering the main surface and side surface of each of the plurality of chips with resin and sealing the chips to form a sealed body. The manufacturing method includes forming a stacked body in which a plurality of sealed bodies are stacked. The plurality of sealed bodies include a first sealed body and a second sealed body. Forming the stacked body includes stacking the second sealed body on the first sealed body in a state where the position of the chip in the second sealed body is offset in a direction in the plane with respect to the position of the chip in the first sealed body.

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Abstract: A method of producing microelectronic components includes forming a functional layer system; applying a laminar carrier to the functional layer system; attaching a workpiece to a workpiece carrier; utilizing incident radiation of a laser beam is focused in a boundary region between a growth substrate and the functional layer system, and a bond between the growth substrate and the functional layer system in the boundary region is weakened or destroyed; separating a functional layer stack from the growth substrate, wherein a vacuum gripper having a sealing zone that circumferentially encloses an inner region is applied to the reverse side of the growth substrate, a negative pressure is generated in the inner region such that separation of the functional layer stack from the growth substrate is initiated in the inner region; and the growth substrate held on the vacuum gripper is removed from the functional layer stack.

Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A method of fabricating a display device, the method comprising: preparing a mother substrate having a first cell region and a second cell region, and a first target region and a second target region in the first cell region and the second cell region, respectively; providing an encapsulation material on a first printing region in the first target region to form a first encapsulation layer; and providing the encapsulation material on a second printing region in the second target region to form a second encapsulation layer, wherein a center of the second printing region is shifted from a center of the second target region in a specific direction.

Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Abstract: Methods for making laser-marked packaged surface acoustic wave devices are provided. The method may include directly marking a surface of a piezoelectric substrate, where the opposite surface of the piezoelectric substrate includes a package structure encapsulating a surface acoustic wave device. The method may include exposing the surface of the piezoelectric substrate to light from a deep ultraviolet laser. By using a wavelength readily absorbed by the piezoelectric substrate, a relatively shallow marking may be made in the piezoelectric substrate. The markings may extend less than 1 micrometer into the piezoelectric substrate, and do not affect the structural integrity of the piezoelectric substrate or the operation of the packaged surface acoustic wave device.

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.