Patents Examined by Jean B. Jeanglaude
  • Patent number: 11569801
    Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: January 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Liang Dai, Kentaro Yamamoto, Behnam Sedighi
  • Patent number: 11569838
    Abstract: A current source and/or current sink digital-to-analog converter (DAC) includes a DAC circuit that converts a digital code to an analog current or voltage signal, an optional transconductance circuit that converts a voltage output of the DAC circuit into a current signal, and an output circuit that amplifies a current output of the DAC circuit or optionally amplifies a current output of the transconductance circuit to set a desired high current output for application to an output of the current source and/or current sink DAC. A power supply control current may be coupled to a power supply circuit that supplies power to the output circuit of the current source and/or current sink DAC. The power supply control current adjusts the output of the power supply circuit to cause the current source and/or current sink DAC to operate at a higher power efficiency.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 31, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventor: Suat Sukuti Tukel
  • Patent number: 11569837
    Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Aram Akhavan, Kentaro Yamamoto, Lei Sun, Ganesh Kiran
  • Patent number: 11563446
    Abstract: Fast, efficient, and robust compression-based methods for detecting boundaries in arbitrary datasets, including sequences (1D datasets), are desired. The methods, each employing three simple algorithms, approximate the information distance between two adjacent sliding windows within a dataset. One of the algorithms calculates an initial ordered list of subsequences; while a second algorithm updates the ordered list of subsequences by dropping a first entry and appending a last entry rather than calculating completely new ordered lists with each iteration. Large values in the distance metric are indicative of boundary locations. A smoothed z-score or a wavelet-based algorithm may then be used to locate peaks in the distance metric, thereby identifying boundary locations. An adaptive version of the method employs a collection of window sizes and corresponding weighting functions, making it more amenable to real datasets with unknown, complex, and changing structures.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 24, 2023
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Christina Ting, Richard V. Field, Jr., Tu-Thach Quach, Travis L. Bauer
  • Patent number: 11562230
    Abstract: New and efficient protocols are provided for privacy-preserving machine learning training (e.g., for linear regression, logistic regression and neural network using the stochastic gradient descent method). A protocols can use the two-server model, where data owners distribute their private data among two non-colluding servers, which train various models on the joint data using secure two-party computation (2PC). New techniques support secure arithmetic operations on shared decimal numbers, and propose MPC-friendly alternatives to non-linear functions, such as sigmoid and softmax.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 24, 2023
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventors: Payman Mohassel, Yupeng Zhang
  • Patent number: 11561738
    Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 24, 2023
    Assignee: Kioxia Corporation
    Inventors: Masato Sumiyoshi, Keiri Nakanishi, Sho Kodama, Kohei Oikawa
  • Patent number: 11562209
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for content recommendation using neural networks. In One aspect, a method includes: receiving context information for an action recommendation from multiple possible actions; processing the context information using a neural network that includes Bayesian neural network layers to generate, for each of the actions, one or more parameters of a distribution over possible action scores for the action, where each parameter for each Bayesian layer is associated with data representing a probability distribution over multiple possible current values for the parameter; for each parameter of each Bayesian neural network layer, selecting the current value for the parameter using data representing probability distribution over possible current values for the parameter; and selecting an action from multiple possible actions using the parameters of the distributions over the possible action scores for the action.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: January 24, 2023
    Assignee: DeepMind Technologies Limited
    Inventors: Charles Blundell, Julien Robert Michel Cornebise
  • Patent number: 11558061
    Abstract: An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 17, 2023
    Assignee: Ciena Corporation
    Inventors: Aravinthan Vigneswaran, Daniel Pollex
  • Patent number: 11552652
    Abstract: Systems and methods for lossless compression of tabular numeric data are provided. The system can include one or more data compression servers executing data compression system code to compress the tabular numeric data, a storage database to store the compressed tabular numeric data, and one or more data decompression servers to decompress the tabular numeric data for use. The one or more data compression servers, the storage database, and the one or more data decompression servers can communicate via a communication network. The system can receive the uncompressed tabular numeric data from one or more data generation systems, processes the uncompressed tabular numeric data with the data compression system code, and generate a compressed table of numeric information, which can be stored in the database, or later decompressed by the one or more data decompression servers.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 10, 2023
    Assignee: Insurance Services Office, Inc.
    Inventor: Ismael Aguilera Martín de Los Santos
  • Patent number: 11552648
    Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: January 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
  • Patent number: 11545996
    Abstract: Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 3, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Roberto Sergio Matteo Maurino, Venkata Aruna Srikanth Nittala, Bhargav R. Vyas, Christopher Peter Hurrell, Andrew J. Thomas
  • Patent number: 11546683
    Abstract: To reduce the effect on the communication performance of an antenna to secure a good communication state with respect to the antenna. An acoustic output device includes a speaker for outputting sound, a cell having one surface facing in a facing direction represented by a predetermined direction, a control board for controlling predetermined parts, and an antenna for sending and receiving signals, the antenna having at least a portion spaced from the control board and the cell. The cell and the control board are positioned side by side with each other in directions different from thicknesswise directions of the control board. The facing direction is different from the directions in which the cell and the control board are side by side with each other. The antenna is positioned side by side with at least one of the control board or the cell in the thicknesswise directions or the facing direction.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 3, 2023
    Assignee: SONY CORPORATION
    Inventors: Keita Sakane, Yoshihisa Kadosawa, Yuki Shimizu
  • Patent number: 11539376
    Abstract: An isolator of embodiments includes a ?? analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 27, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masaki Nishikawa, Shoji Ootaka
  • Patent number: 11532895
    Abstract: A radio frequency module includes a first substrate having a first principal surface and a second principal surface on the opposite side to the first principal surface; a signal terminal which is provided on the first principal surface and through which a signal is transmitted to and received from an external circuit; a power supply terminal that is provided on the second principal surface and is supplied with a power supply signal; an antenna; and a radio frequency electronic component that is electrically connected to the signal terminal, the power supply terminal and the antenna, and controls transmission and reception of the antenna based on the signal and the power supply signal.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: December 20, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hideki Ueda
  • Patent number: 11533062
    Abstract: A non-uniform sampling pADC is disclosed. The pADC may include an optical pulse source configured to generate uniform optic pulses. The pADC may include a non-uniform sampling system. The non-uniform sampling system may include an inter-pulse timing modulation sub-system configured to convert the uniform optic pulses into non-uniform optic pulses. The non-uniform sampling system may include a timing control sub-system configured to control the timing of the optical pulse source. The pADC may include an optical modulator configured to modulate the non-uniform optical pulses. The pADC may include a photodetector configured to convert the modulated non-uniform optic pulses into electronic pulses. The pADC may include a pulse capture assembly configured to capture a pulse amplitude of the electronic pulses and generate sampled radio frequency output pulses. The pADC may include a quantizer configured to quantize the sampled radio frequency output pulses and generate digital radio frequency output signals.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 20, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Wenlu Chen, Oliver S. King, Han Chi Hsieh
  • Patent number: 11527307
    Abstract: Methods, systems, and computer programs for compressing nucleic acid sequence data. A method can include obtaining nucleic acid sequence data representing: (i) a read sequence, and (ii) a plurality of quality scores, determining whether the read sequence includes at least one “N” base, based on a determination that the read sequence does not include at least one “N” base, generating a first encoded data set by using a first encoding process to encode each of the quality scores of the read sequence using a base-(x minus 1) number, where x is an integer representing a number of different quality scores used by the nucleic acid sequencing device, and using a second encoding process to encode the first encoded data set, thereby compressing the data to be compressed.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: December 13, 2022
    Assignee: Illumina, Inc.
    Inventor: Guillaume Alexandre Pascal Rizk
  • Patent number: 11526752
    Abstract: Provided are computing systems and methods directed to active learning and may provide advantages or improvements to active learning applications for skewed data sets. A challenge in training and developing high-quality models for many supervised learning scenarios is obtaining labeled training examples. Provided are systems and methods for active learning on a training dataset that includes both labeled and unlabeled datapoints. In particular, the systems and methods described herein can select (e.g., at each of a number of iterations) a number of the unlabeled datapoints for which labels should be obtained to gain additional labeled datapoints on which to train a machine-learned model (e.g., machine-learned classifier model). Generally, provided are cost-effective methods and systems for selecting data to improve machine-learned models in applications such as the identification of content items in text, images, and/or audio.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: December 13, 2022
    Assignee: GOOGLE LLC
    Inventors: Qi Zhao, Abbas Kazerouni, Sandeep Tata, Jing Xie, Marc Najork
  • Patent number: 11509326
    Abstract: A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 22, 2022
    Assignee: NXP USA, Inc.
    Inventors: Simon Brule, Thierry Dominique Yves Cassagnes, Pascal Sandrez, Soufiane Serser
  • Patent number: 11507826
    Abstract: A computer system uses Learning from Demonstration (LfD) techniques in which a multitude of tasks are demonstrated without requiring careful task set up, labeling, and engineering, and learns multiple modes of behavior from visual data, rather than averaging the multiple modes. As a result, the computer system may be used to control a robot or other system to exhibit the multiple modes of behavior in appropriate circumstances.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 22, 2022
    Assignee: Osaro
    Inventors: Khashayar Rohanimanesh, Aviv Tamar, Yinlam Chow
  • Patent number: 11502696
    Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma