Patents Examined by Jean B. Jeanglaude
  • Patent number: 11962335
    Abstract: Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: April 16, 2024
    Assignee: Google LLC
    Inventor: Reiner Alwyn Pope
  • Patent number: 11955985
    Abstract: An AD converter includes: an integration unit that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator that compares the integrated voltage with the threshold voltages; an integration determination unit that, before the operation of integrating is started, causes the comparator to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit that, when the rough adjustment threshold voltage is smaller than th
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 9, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tadashi Minotani, Kenichi Matsunaga
  • Patent number: 11941527
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a neural network. A method includes: training a neural network having a plurality of network parameters to perform a particular neural network task and to determine trained values of the network parameters using an iterative training process having a plurality of hyperparameters, the method comprising: maintaining a plurality of candidate neural networks and, for each of the candidate neural networks, data specifying: (i) respective values of the network parameters for the candidate neural network, (ii) respective values of the hyperparameters for the candidate neural network, and (iii) a quality measure that measures a performance of the candidate neural network on the particular neural network task; and for each of the plurality of candidate neural networks, repeatedly performing additional training operations.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: March 26, 2024
    Assignee: DeepMind Technologies Limited
    Inventors: Maxwell Elliot Jaderberg, Wojciech Czarnecki, Timothy Frederick Goldie Green, Valentin Clement Dalibard
  • Patent number: 11936396
    Abstract: An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 19, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tadashi Minotani, Kenichi Matsunaga
  • Patent number: 11936111
    Abstract: An antenna array with a layered structure having a base layer with a metamaterial structure, a printed circuit board (PCB) layers, a feed layer arranged on the opposite side of the PCB from the RF IC(s), and a radiating layer arranged on the feed layer. The radiating layer having a plurality of radiating elements. The metamaterial structure is arranged to attenuate electromagnetic radiation propagating between the at least two adjacent waveguides in the frequency band.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 19, 2024
    Assignee: GAPWAVES AB
    Inventors: Thomas Emanuelsson, Yang Jian, Ashraf Uz Zaman, Wai Yan Yong
  • Patent number: 11929758
    Abstract: An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 12, 2024
    Assignee: SEMISOLUTION CO., LTD.
    Inventors: Jung Won Lee, Ji Hyung Kim
  • Patent number: 11928566
    Abstract: There is provided a system and method for compression and decompression of a data stream used by machine learning networks. The method including: encoding each value in the data stream, including: determining a mapping to one of a plurality of non-overlapping ranges, each value encoded as a symbol representative of the range and a corresponding offset; and arithmetically coding the symbol using a probability count; storing a compressed data stream including the arithmetically coded symbols and the corresponding offsets; and decoding the compressed data stream with arithmetic decoding using the probability count, the arithmetic decoded symbols use the offset bits to arrive at a decoded data stream; and communicating the decoded data stream for use by the machine learning networks.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: March 12, 2024
    Inventors: Alberto Delmas Lascorz, Andreas Moshovos
  • Patent number: 11923873
    Abstract: In certain examples, methods and semiconductor structures are directed to an apparatus including a photon emitter such as an LED which operates over an emission wavelength range and a photo-voltaic device arranged relative to the photon emitter to provide index-matched optical coupling between the photo-voltaic device and the photon emitter for an emission wavelength range of the photon emitter.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: March 5, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Shanhui Fan, Bo Zhao, Sid Assawaworrarit, Parthiban Santhanam, Meir Orenstein
  • Patent number: 11923874
    Abstract: Aspects relate to compression of messages in a wireless communication system. For messages, such as ACK/NACK feedback in a communication system, messages having an occurrence above or below a certain number of events (e.g., ACK/NACK events) or a probability of the occurrence may be compressed into a single message. By compressing the messages into a single message, the overhead used to transmit such messages may be reduced.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Huang, Peter Gaal, Juan Montojo, Hwan Joon Kwon
  • Patent number: 11916568
    Abstract: A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Marcel A. Kossel, Pier Andrea Francese, Abdullah Serdar Yonar, Mridula Prathapan, Thomas Morf
  • Patent number: 11916319
    Abstract: Single band and multiband wireless antennas are an important element of wireless systems. Competing tradeoffs of overall footprint, performance aspects such as impedance matching and cost require not only consideration but become significant when multiple antenna elements are employed within a single antenna such as to obtain circular polarization transmit and/or receive. Accordingly, it would be beneficial to provide designers of a wide range of electrical devices and systems with compact single or multiple frequency band antennas which, in addition to providing the controlled radiation pattern and circular polarization purity (where required) are impedance matched without substantially increasing the footprint of the antenna and/or the complexity of the microwave/RF circuit interfaced to them, whilst supporting multiple signals to/from multiple antenna elements in antennas employing them.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: February 27, 2024
    Assignee: Tallysman Wireless Inc.
    Inventors: Mohamed Emara, Julien Hautcoeur, Gyles Panther, Joseph Botros
  • Patent number: 11916316
    Abstract: An RFID tag is provided for transmitting and receiving a communication signal. The RFID tag includes a base material, an antenna pattern disposed on the base material, and a high-loss member. The high-loss member is disposed adjacent to the antenna pattern and has a high loss at a frequency higher than a frequency of the communication signal, compared with the antenna pattern and the base material. When the RFID tag is subjected to an electromagnetic wave heating microwave, the high-loss member generates heat and the antenna pattern is cut at a position of the high-loss member.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 27, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hirokazu Yazaki
  • Patent number: 11909098
    Abstract: An antenna structure includes: a metal plate disposed with a first accommodating groove; an antenna unit including a radiation piece and a coupling piece; and a radio frequency module disposed on a first side of the metal plate and electrically connected to the radiation piece. At least one of the radiation piece and the coupling piece is disposed in the first accommodating groove. The radiation piece is insulated from the metal plate, the coupling piece is insulated from the metal plate, the radiation piece is disposed opposite to the coupling piece and insulated from the coupling piece. The radiation piece is located between the coupling piece and the radio frequency module. The radiation piece is configured to generate a resonance in a first preset band, and the coupling piece is configured to expand the bandwidth of the resonance in the first preset band.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: February 20, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Huanchu Huang, Yijin Wang, Xianjing Jian
  • Patent number: 11909106
    Abstract: A leaning vehicle having a vehicle-to-everything (V2X) communication antenna mounted thereon, a body frame that leans in a vehicle leftward or rightward direction when the leaning vehicle turns left or right, and a V2X communication device configured to perform V2X communication. The V2X communication antenna has such a radiation pattern that a 3 dB beam width thereof in a horizontal mounting plane is larger than the 3 dB beam width thereof in a vertical mounting plane, the 3 dB beam width in the vertical mounting plane existing both in a vehicle upper region and in a vehicle lower region, and the 3 dB beam width in the horizontal mounting plane existing both in a vehicle left region and in a vehicle right region. The V2X communication device performs the V2X communication with another V2X communication device, at least when the leaning vehicle turns left or right and the body frame leans accordingly.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 20, 2024
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Yasushi Hashimoto, Daisuke Asano
  • Patent number: 11888495
    Abstract: An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 30, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Munehiko Nagatani, Teruo Jo, Hiroshi Yamazaki, Hideyuki Nosaka
  • Patent number: 11876519
    Abstract: An oscillation circuit has a first oscillator having output nodes of n stages, where n is an integer of 3 or more, a second oscillator having output nodes of n stages, and a third oscillator having output nodes of n stages. An output node at an a-th stage of the first oscillator and an output node at an a-th stage of the second oscillator are connected with each other, where a is an integer of 1 or more and n or less and an output node at a b-th stage of the second oscillator and an output node at a b-th stage of the third oscillator are connected with each other, where b is an integer of 1 or more and n or less different from a.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 16, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Toyama, Tuan Thanh Ta, Satoshi Kondo, Akihide Sai, Toshiki Sugimoto, Kentaro Yoshioka
  • Patent number: 11876539
    Abstract: A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 16, 2024
    Assignee: AMS INTERNATIONAL AG
    Inventors: Srinidhi Koushik Kanagal Ramesh, Thomas Fröhlich
  • Patent number: 11876540
    Abstract: Example embodiments relate to an ADAS sensor data processing unit, to an ADAS sensor system and to an ADAS sensor data evaluation method for use in driver assistance systems or systems for the automated driving of a vehicle. The ADAS sensor data processing unit includes an input interface, a decompression module, a processing unit and an output unit. The input interface is designed to receive data of an ADAS sensor that have been subjected to lossy compression by a compression module. The decompression module is designed to decompress the compressed data of the ADAS sensor. The processing unit is designed to process the decompressed data (IdSD) of the ADAS sensor, information relevant to an ADAS/AD function being ascertained from the decompressed sensor data. The output unit is designed to output the ascertained information relevant to the ADAS function.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 16, 2024
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Elias Strigel, Stefan Heinrich, Dieter Krökel, Thomas Fechner, Martin Pfitzer, Robert Thiel
  • Patent number: 11876527
    Abstract: An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.
    Type: Grant
    Filed: December 12, 2021
    Date of Patent: January 16, 2024
    Assignee: Skymizer Taiwan Inc.
    Inventors: Wen Li Tang, Shu-Ming Liu, Der-Yu Tsai, Po-Sheng Chang
  • Patent number: 11868025
    Abstract: Apparatuses comprising cascaded or series configurations of Mach-Zehnder electrooptic modulators, where the nonlinearities of the cascaded and series configurations of Mach-Zehnder electrooptic modulators increase signal bandwidth and boost signal fidelity in electronic digital to analog converters. The Mach-Zehnder electrooptic modulators are combined with photodiode detectors that are used to convert signals from the optical domain to the electrical domain.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: January 9, 2024
    Assignee: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC
    Inventors: Ryan D. Muir, Vincent J. Hernandez, Brandon W. Buckley, Daniel E. Mittelberger, John E. Heebner