Abstract: A filter stage system, includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous time baseband filter generates a filtered current, and a mirroring component mirrors the filtered current to an output.

Abstract: An analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.

Abstract: A system and method for data compression with homomorphic encryption, which enables secure storage of private information in a database, and which enables searching and comparison of encrypted data within the database, comprising a stream condition system configured to optimize the contents of received data for lossless compression by a data encoder, a data encoder to perform the lossless compression, and an encrypted search engine configured to encrypt the compressed data according to a homomorphic encryption scheme and store the encrypted data in a database. The system may receive a data query and encrypt the data query according to the homomorphic encryption scheme. The encrypted data query may be compared against an encrypted element in the database and an encryption score generated. The encryption score may be compared against a set of criteria to determine if a match is found. Matched data may be returned to the requesting entity.

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the

Abstract: A bipolar TDC apparatus with a phase detection and signal switching circuitry and a phase error measurement circuitry. The phase detection and signal switching circuitry include a multiplexer and phase detector, together referred to as PD_MUX. The PD_MUX is used to handle the order of the two input signal phases of a TDC, or in other words, to enable TDC the bipolarity detection of the phase error. The apparatus detects first the polarity of the phase error and then prepares the right phase order when they arrive at the TDC measurement elements of the phase error measurement circuitry to ensure that always the earlier one starts the TDC and the later one triggers the measurement event. As such, the phase measurement circuitry (or measurement block) provides the phase error magnitude information, while the PD_MUX provides the sign—polarity information.

Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

Abstract: Systems and methods for lossless compression of tabular numeric data are provided. The system can include one or more data compression servers executing data compression system code to compress the tabular numeric data, a storage database to store the compressed tabular numeric data, and one or more data decompression servers to decompress the tabular numeric data for use. The one or more data compression servers, the storage database, and the one or more data decompression servers can communicate via a communication network. The system can receive the uncompressed tabular numeric data from one or more data generation systems, processes the uncompressed tabular numeric data with the data compression system code, and generate a compressed table of numeric information, which can be stored in the database, or later decompressed by the one or more data decompression servers.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

Abstract: A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

Abstract: Coaxial collinear antenna examples are described. An example coaxial collinear antenna includes a first segment and a second segment of a coaxial cable. The second segment includes a second inner conductor and a second outer conductor. The first inner conductor of the first segment is coupled to the second outer conductor of the second segment. The first outer conductor of the first segment is coupled to the second inner conductor of the second segment. Further, a first wire mesh is attached to the first outer conductor of the first segment, and a second wire mesh is attached to the second outer conductor of the second segment. Additionally, the coaxial collinear antenna includes an end-fed port that is situated at a distal end of the coaxial collinear antenna.

Abstract: Exemplary apparatus can be provided which can include a laser arrangement that is configured to provide a laser radiation, and including an optical cavity. The optical cavity can include a dispersive optical waveguide first arrangement having first and second sides, and which is configured to (i) receive at least one first electro-magnetic radiation at the first side so as to provide at least one second electro-magnetic radiation, and (ii) to receive at least one third electro-magnetic radiation at the second side so as to provide at least one fourth electro-magnetic radiation. The first and second sides are different from one another, and the second and third radiations are related to one another. The optical cavity can also include an active optical modulator second arrangement which can be configured to receive and modulate the fourth radiation so as to provide the first electro-magnetic radiation to the first arrangement.

Abstract: There is provided a metamaterial textile for providing wireless sensor network and method of designing such. The metamaterial textile comprising a sheet of metamaterial textile cut into a comb shape comprising long base with a plurality of metamaterial textile teeth extending along and from the base, wherein a gap is present between every two adjacent teeth, whereby, the metamaterial textile is configured to enable propagation of radio-surface plasmons wave along the metamaterial textile for providing wireless sensor network. The metamaterial textile is configured to control the height of the radio-surface plasmons wave by changing number of the metamaterial textile teeth, and changing dimensions of the metamaterial textile teeth and changing dimensions of the gaps.

Abstract: Certain aspects of the present disclosure provide techniques for measurement encoding and decoding using neural networks to compress and decompress measurement data. One example method generally includes: generating, via each of a plurality of neural network encoders operating on measurement data, a compressed measurement based on a respective portion of the measurement data, wherein each of the neural network encoders is based on the same neural network model; generating at least one message indicative of the measurement data based on the compressed measurements; and transmitting the at least one message.

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the

Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.

Abstract: An apparatus includes a differential current-to-voltage conversion circuit that includes an input sampling stage circuit, a differential integration and DC signal cancellation stage circuit, and an amplification and accumulator stage circuit. An input common mode voltage of the differential current-to-voltage conversion circuit is independent of an output common mode voltage of the differential current-to-voltage conversion circuit.

Abstract: A system, a non-transitory computer readable media and a method for FIR filtering. The method may include obtaining a set of input samples; and concurrently applying a FIR filtering process on the set of input samples to provide a set of FIR filtered output samples. The latter may include calculating intermediate results that represent a first number of coefficient-input sample products, while calculating only some of the first number of coefficient-input sample products, wherein the calculating of the intermediate results is executed by using less than a first number of multipliers.

Abstract: Data compression is continuously optimized using frequency-based dictionary lookup tables for communication between a transmitter in a vehicle and a receiver. In a transmitter, first and second frequency-based dictionary lookup tables are provided. The transmitter receives a data block and compresses it using the first table. Using the data block, the second table is updated and a difference between a compression efficiency of the first table and a compression efficiency of the second table for the data block is calculated. The compressed data block is transmitted to the receiver. When the difference is more than a pre-defined threshold, the content of the first table is replaced with the content of the updated second table in the transmitter. The content of the updated second table is then also transmitted to the receiver.