Abstract: An oscillation circuit has a first oscillator having output nodes of n stages, where n is an integer of 3 or more, a second oscillator having output nodes of n stages, and a third oscillator having output nodes of n stages. An output node at an a-th stage of the first oscillator and an output node at an a-th stage of the second oscillator are connected with each other, where a is an integer of 1 or more and n or less and an output node at a b-th stage of the second oscillator and an output node at a b-th stage of the third oscillator are connected with each other, where b is an integer of 1 or more and n or less different from a.

Abstract: A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

Abstract: Example embodiments relate to an ADAS sensor data processing unit, to an ADAS sensor system and to an ADAS sensor data evaluation method for use in driver assistance systems or systems for the automated driving of a vehicle. The ADAS sensor data processing unit includes an input interface, a decompression module, a processing unit and an output unit. The input interface is designed to receive data of an ADAS sensor that have been subjected to lossy compression by a compression module. The decompression module is designed to decompress the compressed data of the ADAS sensor. The processing unit is designed to process the decompressed data (IdSD) of the ADAS sensor, information relevant to an ADAS/AD function being ascertained from the decompressed sensor data. The output unit is designed to output the ascertained information relevant to the ADAS function.

Abstract: An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.

Abstract: Apparatuses comprising cascaded or series configurations of Mach-Zehnder electrooptic modulators, where the nonlinearities of the cascaded and series configurations of Mach-Zehnder electrooptic modulators increase signal bandwidth and boost signal fidelity in electronic digital to analog converters. The Mach-Zehnder electrooptic modulators are combined with photodiode detectors that are used to convert signals from the optical domain to the electrical domain.

Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

Abstract: An apparatus includes a module comprising an antenna having at least one antenna component. The apparatus further includes at least one tuning component coupled to the at least one antenna component. The at least one tuning component is external to the module.

Abstract: An isolator of embodiments includes a ?? analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

Abstract: A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.

Abstract: New and efficient protocols are provided for privacy-preserving machine learning training (e.g., for linear regression, logistic regression and neural network using the stochastic gradient descent method). A protocols can use the two-server model, where data owners distribute their private data among two non-colluding servers, which train various models on the joint data using secure two-party computation (2PC). New techniques support secure arithmetic operations on shared decimal numbers, and propose MPC-friendly alternatives to non-linear functions, such as sigmoid and softmax.

Abstract: Artificial intelligence (AI) layer-based process extraction for robotic process automation (RPA) is disclosed. Data collected by RPA robots and/or other sources may be analyzed to identify patterns that can be used to suggest or automatically generate RPA workflows. These AI layers may be used to recognize patterns of user or business system processes contained therein. Each AI layer may “sense” different characteristics in the data and be used individually or in concert with other AI layers to suggest RPA workflows.

Abstract: A system and method for data compression with encryption, that produces a conditioned data stream by replacing data blocks within an input data stream to bring the frequency of each data block closer to an ideal value, produces an error stream comprising the differences between the original data and the encrypted data, and compresses the conditioned data.

Abstract: According to one embodiment, a data decompression device includes: a detection circuit configured to detect a boundary between a header and a payload in a compressed stream, based on boundary information in the header; a separation circuit configured to separate the header and the payload; a first decompression circuit configured to decompress a compressed coding table in the header; and a second decompression circuit configured to decompress the payload, based on an output of the first decompression circuit.

Abstract: The present disclosure provides a decoding method, a decoding device, and a readable storage medium, which include performing an exclusive-or logic operation on a first identification bit and a second identification bit in a first bit stream to obtain a first operation result, and processing the first bit stream according to the first operation result to obtain a second bit stream; performing the exclusive-or logic operation on a third identification bit and a fourth identification bit in the second bit stream to obtain a second operation result, and processing the second bit stream according to the second operation result to obtain a third bit stream; and deleting two specific bits in the third bit stream to obtain a decoded bit.

Abstract: A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.

Abstract: A method, computer program, and computer system is provided for compressing a deep neural network model. Weight coefficients associated with a deep neural network are quantize and entropy-coded. The quantized and entropy-coded weight coefficients are locally smoothed. The smoothed weight coefficients are compressed based on applying a variational dropout to the weight coefficients.

Abstract: A method for processing data overflow in a decompression process, includes: decompressing an original text, and detecting whether a data overflow event occurs in the decompression process; in response to detecting the data overflow event, storing first data obtained by decompression in a host cache into a target memory, and closing a data read-in port of a decoding engine; decompressing data which is being decompressed in the decoding engine to obtain second data, and storing the second data into a cache of the decoding engine; calculating a position of the decompressed data in the original text; obtaining, on the basis of the position, data which is not decompressed in the original text, re-decompressing the data which is not decompressed to obtain third data, and storing the second data into the target memory; and splicing the first data, the second data, and the third data to obtain complete decompressed data.

Abstract: A system and method for data compression with genomic encryption, which uses frequency analysis on data blocks within an input data stream to produce a prefix table, representing a first layer of transformation, and which applies a Burrow's-Wheeler transform (BWT) to the data inside the prefix table, representing a second layer of transformation, and which compresses the transformed data. In some implementations, the system and method may further include applying the BWT to a conditioned stream of genomic data, wherein the conditioned stream of genomic data is accompanied by an error stream comprising the differences between the original data and the encrypted data.

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

Abstract: Systems and methods for stream-based compression are described. One example is an encoder of a first device that receives an input stream of bytes including a first byte preceded by one or more second bytes. The encoder may determine to identify a prefix code for the first byte. The encoder may select a prefix code table using the one or more second bytes. The encoder may identify, from the selected prefix code table, the prefix code of the first byte. The encoder may generate an output stream of bytes by replacing the first byte in the input stream with the prefix code of the first byte. The encoder may transmit the output stream from the encoder of the first device to a decoder of a second device. The output stream may have a fewer number of bits than the input stream.