Patents Examined by Jean B. Jeanglaude
  • Patent number: 10707887
    Abstract: The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Wen-Chi Wang
  • Patent number: 10707571
    Abstract: An antenna device for a mobile terminal as well as a mobile terminal is provided. The antenna device includes: a metal battery cover including a plurality of first ground points; a mainboard including a plurality of second ground points; a plurality of antennas coupled to the mainboard; a plurality of first connecting members coupling the plurality of first ground points to the plurality of second ground points; and a plurality of first capacitors coupled between the plurality of first connecting members and the plurality of first ground points respectively.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 7, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Qing Wu
  • Patent number: 10698027
    Abstract: Systems and methods are provided for blended analog-to-digital conversion for digital test and measurement devices. A first-frequency-domain circuit path is configured to generate a first processed digital signal having high fidelity to an analog signal over a first frequency domain. A second-frequency-domain circuit path is configured to generate a second processed digital signal having high fidelity to the analog signal over a second frequency domain. A blended digital signal is generated using the first processed digital signal and the second processed digital signal. The blended digital signal can have high fidelity to the analog signal over multiple frequency domains.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 30, 2020
    Assignee: Liquid Instruments Pty Ltd.
    Inventors: Daniel Anthony Shaddock, Danielle Marie Rawles Wuchenich, Paul Anthony Altin, Timothy Tien-Yue Lam, Max Andrew Gordon Schwenke, Benjamin Paul Coughlan, David Sebastiaan Rabeling
  • Patent number: 10700691
    Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 30, 2020
    Assignee: NXP USA, INC.
    Inventors: Srikanth Jagannathan, Christopher James Micielli, George Rogers Kunnen, Carl Culshaw
  • Patent number: 10690730
    Abstract: Switching circuits controllable to force an input into a circuit and to sense a responsively produced output in multiple ways to produce different combinations of positive and negative polarities of a desired signal and of sources of offsets and 1/f noise. The switching circuits are controlled in a non-ordered time sequence of different combinations of positive and negative polarities of the sources of the offsets and 1/f noise that spreads their energy to a frequency range above the desired signal frequency band. The non-ordered time sequence leaves the polarity of the desired signal unchanged. Uncorrelated delta-sigma modulators may generate the control signal. A DSP processes a resulting spectrum of a digital domain version of the sensed output to measure residual offsets and 1/f noise and adds to an input present at the DSMs a signal equal in magnitude and opposite in sign to the measured residual offsets and 1/f noise.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Eric Kimball
  • Patent number: 10686306
    Abstract: A floor cable channel for positioning a cable line element on an underlying surface and for protecting the cable line element. The floor cable channel includes a first channel element and a second channel element for receiving the cable line element and a connection element connecting the first channel element to the second channel element. The connection element allows a rotational movement of the first channel element relative to the second channel element. The floor cable channel can be brought into a transport position in which the channel elements are parallel to each other and into an operating position in which the channel elements are arranged along their longitudinal axes. In the operating position, the first and second channel elements are in contact at their mutually facing front faces to provide a self-locking of the channel elements relative to each other in the operating position.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 16, 2020
    Assignee: Race Result AG
    Inventors: Konstantin Gaiser, Nikias Klohr
  • Patent number: 10680636
    Abstract: An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: JongPal Kim, Ye Dam Kim, Seung Tak Ryu, Min Jae Seo, Dong Hwan Jin
  • Patent number: 10673449
    Abstract: A digital-to-analog converter has both a plurality of DAC stages and a plurality of dummy stages. Each DAC stage causes a glitch or disturbance to a pair of reference voltages when the DAC stage changes its switching state. Each dummy stage also causes a similar glitch or disturbance to the pair of reference voltages when the dummy stage changes its switching state. The dummy stages are controlled to change their switching state responsive to how many DAC stages change their switching state such that a total glitch induced onto the reference voltages remains substantially constant across a succession of digital words converted by the digital-to-analog converter into an analog output signal.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 2, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chien-Chung Yang, Dongyang Tang, Vijayakumar Dhanasekaran
  • Patent number: 10673460
    Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Girish Gopala Kurup, Matthias Klein, Anthony Thomas Sofia, Jonathan D. Bradbury, Ashutosh Misra, Christian Jacobi, Deepankar Bhattacharjee
  • Patent number: 10666279
    Abstract: A circuit includes a phase control logic, an analog-to-digital converter (ADC), and digital logic. The phase control logic is configured to couple to a plurality of power phases of a multi-phase power supply. The digital logic is configured to couple to the phase control logic and the ADC, to receive an instruction to operate in a self-calibration mode of operation, receive a first message including a value associated with a calibrated load configured to couple to the plurality of power phases, perform a self-calibration sub-routine for each power phase of the plurality of power phases based at least partially on the received instruction, the received first message, and a signal received from the ADC, and receive a second message instructing the digital logic to store a result of the self-calibration in a memory of the circuit.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew John Ascher Schurmann, Mayank Jain, Wenkai Wu, Preetam Charan Anand Tadeparthy, Kuang-Yao Cheng
  • Patent number: 10666282
    Abstract: There is provided a transmission device configured to serialize data of a change amount that is based on a signal acquired from a sensor, and transmit the data by simplex communication.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventors: Hiromasa Masuda, Naoki Komine, Hirokazu Yasuda
  • Patent number: 10651871
    Abstract: Systems and methods for stream-based compression include an encoder of a first device that receives an input stream of bytes including a first byte preceded by one or more second bytes. The encoder may determine to identify a prefix code for the first byte. The encoder may select a prefix code table using the one or more second bytes. The encoder may identify, from the selected prefix code table, the prefix code of the first byte. The encoder may generate an output stream of bytes by replacing the first byte in the input stream with the prefix code of the first byte. The encoder may transmit the output stream from the encoder of the first device to a decoder of a second device. The output stream may have a fewer number of bits than the input stream.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 12, 2020
    Assignee: Citrix Systems, Inc.
    Inventor: Muhammad Dawood
  • Patent number: 10642227
    Abstract: A digital-to-time converter (DTC) includes a plurality of delay stages connected in series, in which each of the plurality of delay stages includes an input circuit and a delay circuit. The input circuit has a first input terminal, a second input terminal and a first output terminal, and is configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit. The delay circuit is coupled to the input circuit in series, and is configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal. The delay signal indicates a time interval corresponding to the digital control signal.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 10641799
    Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), and compensator for a voltage regulator (VR), are provided. In one example, an apparatus includes: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, J. Keith Hodgson, Alexander Lyakhov, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan
  • Patent number: 10637490
    Abstract: Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 28, 2020
    Inventor: Alexei V. Nikitin
  • Patent number: 10630310
    Abstract: An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventors: Alphons Litjes, Erik Olieman, Ibrahim Candan
  • Patent number: 10630312
    Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general-purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performed by the instruction being a compression function or a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Matthias Klein, Timothy Slegel, Mark S. Farrell, Anthony T. Sofia, Simon Weishaupt, Ashutosh Mishra
  • Patent number: 10630307
    Abstract: An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Robert S. Jones, III, Tao Chen, Colin McAndrew
  • Patent number: 10623011
    Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.
    Type: Grant
    Filed: May 4, 2019
    Date of Patent: April 14, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Hua-Chun Tseng, Tu-Hsiu Wang
  • Patent number: 10623013
    Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vishnu Ravinuthula, Kyl Wayne Scott