Patents Examined by Jean B. Jeanglaude
  • Patent number: 10511324
    Abstract: A highly programmable data processing unit includes multiple processing units for processing streams of information, such as network packets or storage packets. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. The data processing unit is configured to retrieve speculative probability values for range coding a plurality of bits with a single read instruction to an on-chip memory that stores a table of probability values. The data processing unit is configured to store state information used for context-coding packets of a data stream so that the state information is available after switching between data streams.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 17, 2019
    Assignee: Fungible, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Gurumani Senthil Nayakam
  • Patent number: 10511325
    Abstract: Aspects of dynamic data compression selection are presented. In an example method, as uncompressed data chunks of a data stream are compressed, at least one performance factor affecting selection of one of multiple compression algorithms for the uncompressed data chunks of the data stream may be determined. Each of the multiple compression algorithms may facilitate a different expected compression ratio. One of the multiple compression algorithms may be selected separately for each uncompressed data chunk of the data stream based on the at least one performance factor. Each uncompressed data chunk may be compressed using the selected one of the multiple compression algorithms for the uncompressed data chunk.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 17, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Young Jin Nam, Aaron James Dailey, John Forte
  • Patent number: 10505561
    Abstract: A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 10, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Rares Bodnar, Asif Ahmad, Christopher Peter Hurrell
  • Patent number: 10505276
    Abstract: A wireless communication assembly includes: a primary support member defining a primary mounting surface with first and second electrical contacts; an antenna, adjacent to primary mounting surface perimeter, and a baseband controller, on the primary support member; primary signal paths between the baseband controller and the first contacts; primary feed lines between the second contacts and the antenna; a secondary support member carrying a radio controller and defining a secondary mounting surface with third electrical contacts and ports adjacent to a perimeter of the secondary mounting surface; secondary signal paths between the third contacts and the radio controller; secondary feed lines between the radio controller and the ports; the secondary mounting surface configured to engage with the primary mounting surface to connect the first contacts with the third contacts, and the second contacts with the ports.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 10, 2019
    Assignee: PERASO TECHNOLOGIES INC.
    Inventor: Atabak Rashidian
  • Patent number: 10503122
    Abstract: Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: December 10, 2019
    Assignee: Innophase, Inc.
    Inventor: Nicolo Testi
  • Patent number: 10506736
    Abstract: A remote radio unit, which includes a housing, a ventilation air channel, and a circuit component, where the housing is a sealed hollow cavity; the ventilation air channel passes through the housing, a top end of the ventilation air channel is connected to a top end surface of the housing in a sealed manner, and a bottom end of the ventilation air channel is connected to a bottom end surface of the housing in a sealed manner; and the circuit component is disposed inside the cavity, and is in contact with an external surface of a side wall of the ventilation air channel, so that heat generated by the circuit component is dissipated through the ventilation air channel.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 10, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yong Zheng, Bin Wang, Fei Bian
  • Patent number: 10498321
    Abstract: An imaging device for improving the determining speed of the comparator and reducing power consumption. The comparator includes a differential input circuit that operates with a first power supply voltage, the differential input circuit that outputs a signal when an input signal is higher than a reference signal in voltage, a positive feedback circuit that operates with a second power supply voltage lower than the first power supply voltage and accelerates transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, based on the output signal of the differential input circuit, and a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 3, 2019
    Assignee: SONY CORPORATION
    Inventors: Hidekazu Kikuchi, Tadayuki Taura, Masaki Sakakibara
  • Patent number: 10498567
    Abstract: Examples described herein provide a communication scheme between integrated circuit (IC) dies. In an example, an IC package includes a first IC die and a second IC die. The first IC die includes an encoder/decoder configured to implement encoded communications. The second IC die includes a transceiver configured to implement unencoded differential communications. The encoder/decoder is communicatively coupled to the transceiver. The encoder/decoder is configured to implement communications to the transceiver using a subset of a code map of the encoded communications.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 3, 2019
    Assignee: XILINX, INC.
    Inventor: Alireza S. Kaviani
  • Patent number: 10491237
    Abstract: A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 26, 2019
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Chulwoo Kim, Chaekang Lim
  • Patent number: 10491234
    Abstract: A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 26, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manish Bhardwaj, Devin Allen Cottier, David Peter Foley
  • Patent number: 10491229
    Abstract: The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 26, 2019
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Wen-Chi Wang
  • Patent number: 10468754
    Abstract: The present technology relates to a multiband antenna for wireless mobile communication devices such as cellular telephones. The antenna may include a bifurcated ring structure along one, two, three or all four edges of the device. The ring structure may include bifurcated metal conductors, or bars, extending along the length of the one or more edges.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 5, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventor: Kiran Vanjani
  • Patent number: 10461866
    Abstract: In a modulation system that modulates and transmits an optical signal over at least one optical fiber in response to an input digital data word of N bits, there is an input enabled for receiving the digital data word; an electrically controllable modulator having one or more waveguide branches, where each branch receives an input of an unmodulated optical signal; and a digital to digital converter enabled for converting the N bits to a digital drive vector corresponding to M drive voltage values, where M>N and N>1. The electrically controllable modulator couples the drive voltage values to the unmodulated optical signal(s). The coupling enables pulse modulation of the unmodulated optical signal(s) thereby generating pulse modulated optical signal(s). The electrically controllable modulator outputs the pulse modulated optical signal(s) to one or more outputs that are enabled for transmitting the pulse modulated optical signal(s) over at least one optical fiber.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 29, 2019
    Assignee: Ramot at Tel-Aviv University Ltd.
    Inventors: Yossef Ehrlichman, Ofer Amrani, Shlomo Ruschin
  • Patent number: 10461761
    Abstract: An analog-to-digital converter (ADC) is disclosed. The ADC includes a successive approximation register and a voltage-to-time conversion element. The successive approximation register is configured to receive an input signal and to generate a first digital signal and a residue voltage. The voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. The voltage-to-time conversion element includes an amplifier having an input coupled to an output of the successive approximation register and configured to receive the residue voltage, and a zero crossing detector directly coupled to an output of the amplifier. A time-to-digital converter is coupled to an output of the zero crossing detector and is configured to generate a second digital signal.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 10454492
    Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Akira Shikata, Junhua Shen, Anping Liu
  • Patent number: 10454160
    Abstract: There is provided an antenna device configured to be shaped as a sheet. The antenna device includes an antenna portion provided on one surface of the sheet and configured to implement at least one of transmission of a transmission wave and reception of a reflected wave from a target, and an absorption unit provided on the other surface of the sheet and configured to absorb spurious.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 22, 2019
    Assignee: DENSO TEN Limited
    Inventor: Takahiro Shinojima
  • Patent number: 10447292
    Abstract: Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Burt Lee Price
  • Patent number: 10448538
    Abstract: The disclosed wireless router may include (i) an enclosure, (ii) an antenna, (iii) a printed circuit board assembly, (iv) a radiative heat sink disposed between the antenna and the printed circuit board assembly within the wireless router such that the radiative heat sink is configured to shield the antenna from spurious emissions generated by the printed circuit board assembly, and (v) a fan disposed at a center of the radiative heat sink such that the fan is configured to cool the wireless router by circulating air within the enclosure rather than pushing air through venting in the enclosure. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: December 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Symantec Corporation
    Inventors: Christopher Gaul, Michel Billard, Paul Roybal
  • Patent number: 10424969
    Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 24, 2019
    Assignee: NuCurrent, Inc.
    Inventors: Alberto Peralta, Md. Nazmul Alam, Vinit Singh, Sina Haji Alizad
  • Patent number: 10419021
    Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 17, 2019
    Assignee: Realtime Data, LLC
    Inventors: James J. Fallon, Paul F. Pickel, Stephen J. McErlain, Carlton J. Melone, II