Patents Examined by Jean B. Jeanglaude
  • Patent number: 10615820
    Abstract: A continuous time delta sigma modulator is described in this application. In one example, the continuous time delta sigma modulator includes: a quantizer, a buffer module, a randomizer, and a reference module. The quantizer includes a comparator that generates a digital output based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module stores the digital output for a predetermined delay period and outputs the digital output after the predetermined delay period as a delayed digital output. The randomizer randomizes the delayed digital output to generate a randomized digital output. The reference module modifies the reference potential based on the randomized digital output.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bei-Shing Lien, Jaw-Juinn Horng, Tai-cheng Kee, Pang-yen Chin
  • Patent number: 10608658
    Abstract: A pipelined ADC includes a first sub ADC and a second sub ADC. The second sub ADC is configured to receive, as an input, an analog residue generated by the first sub ADC. The first sub ADC is configured to operate in a first conversion phase, generating a digital output of the first sub ADC, and a second conversion phase, generating the analog residue. The first sub ADC includes a reference-voltage generator circuit configured to generate a reference voltage of the first sub ADC and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage is less than in the first mode of operation. The reference-voltage generator circuit is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: March 31, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Mattias Palm, Daniele Mastantuono, Roland Strandberg
  • Patent number: 10608598
    Abstract: In an example aspect, an apparatus includes a balanced power amplifier, which performs amplification in the presence of a variable antenna impedance. The balanced power amplifier includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Chuan Wang, Li Liu, Kevin Hsi Huai Wang, Bhushan Shanti Asuri, Gurkanwal Sahota, Francesco Carrara
  • Patent number: 10601436
    Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 24, 2020
    Assignee: OLYMPUS CORPORATION
    Inventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa
  • Patent number: 10601435
    Abstract: A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 24, 2020
    Assignee: MEDIATEK INC.
    Inventor: Wei-Hao Tsai
  • Patent number: 10594330
    Abstract: Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Francesco Conzatti, Patrick Torta, Lukas Doerrer, Marco Bresciani, Claus Kropf
  • Patent number: 10594035
    Abstract: Proximity sensing antenna systems include two metallic antenna arms. One antenna arm is connected to an RF transmitter at a radio frequency (RF) feed port, and the other antenna arm is connected to an RF detector (e.g., RF measurement receiver or RF power detector) at an RF sense port. The metallic antenna arms are symmetrically positioned with respect to each other across one or more symmetry axes. The metallic antenna arms can be implemented as inverted-L antennas, dipole antennas, inverted-F antennas, and/or as other antenna arm configurations. Further, the antenna arms can be dimensionally identical and positioned symmetrically about one or more symmetry axes. The antenna system can be used within proximity sensing devices for a wide variety of applications including low power sensing and can also be used for wireless data communication.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 17, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Emil F. Buskgaard, Olfert P. Paulsen
  • Patent number: 10594332
    Abstract: A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Huan Lei, Jian-Ru Lin, Shih-Hsiung Huang
  • Patent number: 10594331
    Abstract: An analog-to-digital conversion device according to one or more embodiments independently executes each of events instructed by a host device. Each of two or more analog-to-digital converters include an execution control unit, an event management unit that notifies of a synchronization instruction when a synchronous conversion event set up with a synchronous conversion operation is instructed as the event, and an operation control unit.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 17, 2020
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Hideki Hayashi, Yoshitaka Takemoto
  • Patent number: 10587281
    Abstract: A system and method for sampling an RF signal uses a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 10, 2020
    Assignee: Maxlinear Asia Singapore PTE LTD
    Inventors: William Michael Lye, Anthony Eugene Zortea, Jatinder Chana
  • Patent number: 10574255
    Abstract: A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 25, 2020
    Assignee: IMEC vzw
    Inventors: Benjamin Hershberg, Jan Craninckx, Ewout Martens
  • Patent number: 10574251
    Abstract: One example includes a Josephson analog-to-digital converter (ADC) system. The system includes a control line inductively coupled to an input signal line on which an input analog signal is provided. The input signal line can be inductively coupled to the control line to propagate an induced input current that is based on the input analog signal on the control line. The system also includes at least one Josephson transmission line (JTL) stage that is biased via a DC bias current and is configured to generate an output pulse in response to the induced input current and the DC bias current exceeding a predetermined threshold current associated with the at least one JTL stage.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 25, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Micah John Atman Stoutimore, Timothy A. Manning, Mark E. Nowakowski, Alexander Marakov
  • Patent number: 10574256
    Abstract: This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement (102) receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator (101) receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp (103), capacitance (104) and switch network (105). In the first mode the op-amp (103) is enabled, and coupled with the capacitance (104) to provide the active filter.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 25, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 10566686
    Abstract: A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 18, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: John F. Kaeding, Owen R. Fay
  • Patent number: 10566984
    Abstract: A signal processing circuit with high noise resistance is realized. The signal processing circuit includes: a first pre-stage circuit that includes a first input terminal; and a second pre-stage circuit that includes a second input terminal. A resistive element with one end connected to the first input terminal and a capacitative element with one electrode connected to the ground are provided in the first pre-stage circuit. The other end of the first resistive element and the other electrode of the first capacitative element are connected to each other. An output node of the first pre-stage circuit and an output node of the second pre-stage circuit are connected to a post-stage circuit.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: February 18, 2020
    Assignee: OMRON Corporation
    Inventor: Yoshitaka Kikunaga
  • Patent number: 10566987
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10566997
    Abstract: A data compression apparatus includes a lossy compression unit for calculating, in advance, a reference error vector magnitude depending on lossy compression and decompression by removing lower bits from a data signal composed of bitstreams, for setting removal target lower bits satisfying a preset error vector magnitude requirement, and for lossily compressing the data signal by removing the removal target lower bits from the data signal, and a communication unit for transmitting the compressed data signal to a data decompression apparatus.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 18, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Je-Won Lee, Eun-Hee Hyun, Heung-Mook Kim, Joon-Young Jung
  • Patent number: 10554212
    Abstract: Circuitry for voltage-to-current conversion, and in particular to differential voltage-to-current conversion circuitry. Such circuitry is operable to receive a differential voltage input signal and output a corresponding differential current signal. First and second controllable current sinks are connected to first and second load nodes of the circuitry so as to draw corresponding sink currents from those nodes.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: February 4, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Frank Werner, Uwe Zillmann, Guido Dröge, André Schäfer
  • Patent number: 10554218
    Abstract: A sigma-delta modulator and method for converting an input voltage such as an analog signal into a digital signal is presented. The modulator may be used as an analog-to-digital converter (ADC). The modulator has a plurality of bias transistors with at least one p-type transistor and at least one n-type transistor. The modulator receives a bias voltage, wherein each bias transistor receives the same bias voltage. This sigma-delta modulator results in reduced power consumption.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventor: Petrus Hendrikus Seesink
  • Patent number: 10554214
    Abstract: A non-linearity evaluation circuit for use with a signal generator having at least a partly non-linear operation. The non-linearity evaluation circuit may include a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, a time position of the amplitude attribute in the target signal defining a time location of a snapshot time window relative to the target signal, a part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and a presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator. The non-linearity evaluation circuit may further include a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: February 4, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Niklas Linkewitsch, Charles Joseph Dedic