Patents Examined by Jean B. Jeanglaude
  • Patent number: 10545462
    Abstract: A time-to-voltage converter (TVC) that can include a timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the timer IC. A switch can be configured to, under control of an output signal of the timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the timer IC is reset indicates a time interval corresponding to the start and stop signals.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: January 28, 2020
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad Taher Abuelma'Atti
  • Patent number: 10547319
    Abstract: Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 28, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Ahmed Mohamed Abdelatty Ali, Paridhi Gulati
  • Patent number: 10541708
    Abstract: A code decompression engine reads compressed code from a memory containing a compressed code part and a dictionary part. The compressed code part contains a series of instructions being either an uncompressed instruction preceded by an uncompressed code bit, or a compressed instruction having a compressed code bit followed by a number of segments field followed by segments, followed by a directory index indication a directory location to read. Each segment consists of a mask type, a mask offset, and a mask.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 21, 2020
    Assignee: Redpine Signals, Inc.
    Inventors: Subba Reddy Kallam, Sriram Mudulodu
  • Patent number: 10541702
    Abstract: Input stages for an analog to digital converter wherein charge for charging parasitic capacitances in the input stage, and particularly in the input switch is sourced from a node which means that it does not have to pass through the input RC filter. This has the effect that the input RC filter can be of lower bandwidth, and/or have a larger resistor value, with the consequent result that there is lower power dissipation in the ADC drive circuitry. In one example this effect is realized by providing a separate input into which charge to charge the parasitic capacitances can be fed from external circuitry. In another example an operational amplifier having high (ideally infinite) input impedance can be used to feed charge to the input switch from the input to the RC filter, or from the node between the resistor and capacitor of the filter, again without unsettling the filter.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: January 21, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Rares Andrei Bodnar, Christopher Peter Hurrell
  • Patent number: 10536160
    Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Lung Chen, Shih-Hsiung Huang, Chien-Ming Wu, Jie-Fan Lai
  • Patent number: 10536158
    Abstract: An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 14, 2020
    Assignee: ANALOG VALUE LTD.
    Inventors: Tiberlu Galambos, Vladimir Koifman, Anatoli Mordakhay
  • Patent number: 10536155
    Abstract: An ADC can include a plurality of time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC can have interleaving errors, since the time-interleaved ADCs in the ADC are not always perfectly matched. One way to calibrate for these mismatches is by observing the digital output signals of the time-interleaved ADCs in the background, or more broadly, without knowledge of the input signal to the ADC (often referred to as “blind” calibration). Due to the nature of these calibrations, the performance of the calibration would significantly degrade when the input signal has certain problematic input conditions, such as a certain coherent input frequency. To address this issue, the data being used for calibration of interleaving errors can go through a qualifying process to assess whether to update error estimates based on the data.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 14, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventor: Eric Otte
  • Patent number: 10528488
    Abstract: A method for efficient name coding in a storage system is provided. The method includes identifying common prefixes, common suffixes, and midsections of a plurality of strings in the storage system, and writing the common prefixes, midsections and common suffixes to a string table in the storage system. The method includes encoding each string of the plurality of strings as to position in the string table of prefix, midsection and suffix of the string, and writing the encoding of each string to memory in the storage system for the plurality of strings, in the storage system.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Robert Lee, Cary A. Sandvig
  • Patent number: 10528010
    Abstract: A time-to-voltage converter (TVC) including a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: January 7, 2020
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad Taher Abuelma'Atti
  • Patent number: 10530382
    Abstract: An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Weiran Kong, Bin Zhang
  • Patent number: 10530381
    Abstract: An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Jie-Fan Lai, Chih-Lung Chen, Shih-Hsiung Huang, Chien-Ming Wu
  • Patent number: 10530037
    Abstract: An antenna device capable of suppressing influence on an antenna performance even if an electronic device is provided in its vicinity is provided. An antenna device 1 is equipped with a top element 30 and a coil 40. A casing 51 of a camera 50 is disposed at such a position as not to be right under the top element 30. The coil 40 is disposed close to the casing 51 in a front-rear direction. A distance between the casing 51 and the coil 40 in the front-rear direction is longer than or equal to 0.00075 times a shortest wavelength of a reception target signal. A maximum antenna efficiency of the antenna device 1 in a predetermined frequency band is higher than or equal to 85% of a maximum antenna efficiency in a case where the camera 50 is not provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 7, 2020
    Assignee: YOKOWO CO., LTD.
    Inventors: Hirotoshi Mizuno, Kentaro Hayashi, Masayuki Goto
  • Patent number: 10530050
    Abstract: Selectively shielded radio frequency modules are disclosed. A radio frequency module can include a package substrate, a radio frequency component on the package substrate, a multi-layer antenna, a radio frequency shielding structure configured to provide shielding between the multi-layer antenna and the radio frequency component. The radio frequency shielding structure can include a shielding layer providing a shield over the radio frequency component and leaving the radio frequency module unshielded over the antenna.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 7, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury, René Rodríguez
  • Patent number: 10523231
    Abstract: A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 31, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Aditya KrishnaSwamy Nurani, Shagun Dusad, Visvesvaraya Appala Pentakota
  • Patent number: 10523227
    Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 31, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhide Takase, Yasuyuki Matsuya, Eri Mizukami, Yuji Inagaki, Kazuki Mizukami, Nozomi Watanabe, Riku Yonekawa
  • Patent number: 10516408
    Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 24, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Rares Bodnar, Asif Ahmad, Christopher Peter Hurrell
  • Patent number: 10516412
    Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shahin Mehdizad Taleie, Ashok Swaminathan, Sudharsan Kanagaraj, Negar Rashidi, Siyu Yang, Behnam Sedighi, Honghao Ji, Jaswinder Singh, Andrew Weil, Dongwon Seo, Xilin Liu
  • Patent number: 10511322
    Abstract: A high-speed digital transmitter for wireless communication systems includes a plurality of transmitter chain circuits configured to respectively receive incoming component signals having a first frequency and to produce outgoing transmission signals having a second frequency greater than the first frequency in a first domain. In some aspects, the incoming component signals are up-sampled to the second frequency using a plurality of streams processed concurrently at a predetermined sample rate over a predetermined number of interpolation filter stages in each of the plurality of transmitter chain circuits. The high-speed digital transmitter also includes a serializer configured to combine the outgoing transmission signals from the plurality of transmitter chain circuits into a serialized transmission signal having a third frequency greater than the second frequency in a second domain different from the first domain.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 17, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Federico Santiago Cattivelli, Gozde Sahinoglu, Vincent Yves Francois Roussel, Zhiheng Cao, Mengan Pan
  • Patent number: 10511323
    Abstract: An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Apple Inc.
    Inventors: Tao Mai, Simone Gambini
  • Patent number: 10511316
    Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 17, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Rares Bodnar, Roberto S. Maurino, Christopher Peter Hurrell, Asif Ahmad