Abstract: Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

Abstract: A disclosed information handling system includes an edge device communicatively coupled to a cloud computing resource. The edge device is configured to respond to receiving, from an internet of things (IoT) unit, a numeric value for a parameter of interest by determining a compressed encoding for the numeric value in accordance with a non-lossless compression algorithm. The edge device transmits the compressed encoding of the numeric value to the cloud computing resource. The cloud computing resource includes a decoder communicatively coupled to the encoder and configured to respond to receiving the compressed encoding by generating a surrogate for the numeric value. The surrogate may be generated in accordance with a probability distribution applicable to the parameter of interest. The compression algorithm may be a clustering algorithm such as a k-means clustering algorithm.

Abstract: Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

Abstract: Techniques are provided for implementing additional compression for existing compressed data. Format information stored within a data block is evaluated to determine whether the data block is compressed or uncompressed. In response to the data block being compressed according to a first compression format, the data block is decompressed using the format information. The data block is compressed with one or more other data blocks to create compressed data having a second compression format different than the first compression format.

Abstract: Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.

Abstract: There is provided a computer implemented method of compressing a baseline dataset comprising a sequence of a plurality of instances of a plurality of unique data elements, the method comprising: providing a weight function that calculates an increasing value for a weight for each one of the plurality of instances of each one of the plurality of unique data elements in the baseline dataset, as a function of increasing number of previously processed sequential locations of each of the plurality of instances of each respective unique data element within the baseline dataset relative to a current sequential location of the baseline dataset, computing an encoding for the baseline dataset according to a distribution of the weight function computed for the plurality of unique data elements in the baseline dataset, and creating a compressed dataset according to the encoding.

Abstract: An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

Abstract: An example radio frequency (RF) front-end module is described, which may include a printed circuit board (PCB) including a ground plane, an RF integrated circuit (RFIC) including RF components mounted on the PCB, and an antenna array on the PCB. The antenna array may operate at a first resonant frequency in a wireless communication network. Further, the RF front-end module may include a slot defined in the ground plane to provide a second resonant frequency in the wireless communication network. The second resonant frequency is lower than the first resonant frequency.

Abstract: A data compressor a zero-value remover, a zero bit mask generator, a non-zero values packer, and a row-pointer generator. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask for a predetermined number of values of each bit stream in which each zero bit mask indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. The non-zero values packer receives the 2N non-zero-value bit streams and forms a group of packed non-zero values. The row-pointer generator that generates a row-pointer for each group of packed non-zero values.

Abstract: Co-clustering of at least some parameters is employed to reduce data transferred between edge and cloud resources. Single-parameter cluster information, including cluster counts, for each of two or more parameters of interest is accessed. Each parameter may represent a time series of numeric values sent from an IoT unit to an edge device. A co-clustering ratio is determined for each unique parameter pair. The co-clustering ratio indicates whether the number of clusters produced by a co-clustering algorithm applied to a group of parameters is less than the number of clusters required to represent the parameters without co-clustering. Co-cluster groups may be identified based on the cluster ratios. For each co-cluster group, the co-clustering algorithm may be invoked to produce compressed encodings of numeric value tuples. The compressed encoding is then transmitted to a cloud computing resource and decoded into a tuple of surrogate values.

Abstract: In a system for converting digital data into a modulated optical signal, an electrically controllable device, including a modulator having one or more actuating electrodes, provides an analog-modulated optical signal that is modulated in response to output data bits of a digital-to-digital mapping. A digital-to-digital conversion provides the mapping of input data words to the output data bits. The mapping enables adjustments to correct for non-linearities and other undesirable characteristics, thereby improving signal quality.

Abstract: An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

Abstract: A system comprises an encoder configured to entropy encode a bitstream comprising both compressible and non-compressible symbols. The encoder parses the bitstream into a compressible symbol sub-stream and a non-compressible sub-stream. The non-compressible symbol sub-stream bypass an entropy encoding component of the encoder while the compressible symbol sub-stream is entropy encoded. When a quantity of bytes of entropy encoded symbols and bypass symbols is accumulated a chunk of fixed or known size is formed using the accumulated entropy encoded symbol bytes and the bypass bytes without waiting on the full bitstream to be processed by the encoder. In a complementary manner, a decoder reconstructs the bitstream from the packets or chunks.

Abstract: A weight data compression method includes: generating a 4-bit data string of 4-bit data items each expressed as any one of nine 4-bit values, by dividing ternary weight data into data items each having 4 bits; and generating first compressed data including a first flag value string and a first non-zero value string by (i) generating the first flag value string by assigning one of 0 and 1 as a first flag value of a 1-bit flag to a 4-bit data item 0000 and assigning an other of 0 and 1 as a second flag value of the 1-bit flag to a 4-bit data item other than 0000 among the 4-bit data items in the 4-bit data string and (ii) generating the first non-zero value string by converting the 4-bit data item other than 0000 into a 3-bit data item having any one of eight 3-bit values.

Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a se

Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Abstract: A device, which includes an input, configured to read in an analog signal, an analog/digital converter, configured to convert the analog signal into a digital value, and a processor, configured to determine a digital measured value. The processor is further configured to derive a calibrated digital value from the digital value with the aid of a linear calibration function and to derive the digital measured value from the calibrated digital value with the aid of a nonlinear measurement function. The processor modifies the linear calibration function in response to a calibration signal, based on an algorithm, which is based on the nonlinear measurement function, and a number of predefined comparison measured values.

Abstract: An apparatus and associated method are provided involving a housing having a periphery configured to operate as a second antenna, a third antenna, and a fourth antenna. The periphery includes a top wall having a first slot formed therein, a first side wall having a second slot formed therein, and a second side wall having a third slot formed therein. The top wall is arranged between the first side wall and the second side wall, and a top portion of the periphery is defined between the second slot and the third slot. The top portion is divided into a first top side portion and a second top side portion via the first slot. Further, the first top side portion operates as the second antenna, and the second top side portion operates as both the third antenna and the fourth antenna.

Abstract: Communications method and apparatus include encoding information into a high-peakedness designed pulse train, converting the designed pulse train into a low-peakedness signal suitable for modulating a narrowband carrier to generate a physical communication signal with desired spectral and temporal properties, and generating and transmitting the physical communication signal. The communications method and apparatus also include receiving and demodulating the physical communication signal, and further converting the demodulated signal into a high-peakedness received pulse train corresponding to the designed pulse train, so that the encoded information may be extracted from the received pulse train.

Abstract: A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.