Patents Examined by Jeffrey T. Knapp
  • Patent number: 5653379
    Abstract: Ceramic to metal stock or substrates having a relatively large and thick metal core and a relatively thin ceramic layer or layers are bonded to the metal core or a selected portion thereof by providing a metal core material having a temperature coefficient of expansion which is tailored to the temperature coefficient of expansion of the ceramic layer to be bonded thereto. The typical core materials include multilayer composite metal laminates embodying Cu/Mo/Cu, Cu/Kovar/Cu, Cu/Invar/Cu and the like and including powdered metal composites embodying Cu-W, Ag-Mo, Ag-W, Al-Si, Cu/Mo/Cu, Cu/Kovar/Cu, SiC-Cu, Ni-Fe alloys having from about 20% Ni to about 80% Ni, etc. The ceramic layer is chosen primarily for the properties of dielectric strength and isolation properties and typically include such ceramics as alumina, beryllium oxide, aluminum nitride, silicon carbide, etc.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James Forster, Premkumar Hingorany, Henry F. Breit
  • Patent number: 5653377
    Abstract: Method of attaching an insert to a valve seat location of an engine involves forming an engine valve seat location with a circular conical face surface constituted of a light metal; forming an insert with a circular conical bonding surface for mating with the face surface, the bonding surface being constituted of a metal dissimilar to the light metal and having a higher hardness and a higher melting temperature than the light metal of the face surface; aligning the axes of the face surface and bonding surface and gradually rotationally driving the insert into the valve seat with sufficient pressure and for a controlled period of time frictionally melt or plasticize a film of the face surface; and thereafter ceasing the rotational driving while holding the surfaces together with sufficient forging pressure and for a period of time to allow the melted film to recrystallize and create a metallurgical bond between the surfaces.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: August 5, 1997
    Assignee: Ford Motor Company
    Inventors: Larry V. Reatherford, Stephen G. Russ
  • Patent number: 5651493
    Abstract: A method for analyzing solder joint assemblies in devices such as solder bumped silicon chips, ball grid arrays or land grid arrays is disclosed. The method includes applying a dye solution to a device under test and then causing that dye solution to penetrate any interstices between any solder interconnect and the device under test, which also includes penetrating any fractures in any joints or joint failures. Next, the dye is dried or cured so as to provide ready analysis upon the analysis portion of the method. The device under test is then caused to be separated or fractured in such a way that a seam or border of a solder joint or an attachment border may be analyzed to identify any structural failure by visually analyzing where any dye has penetrated such structural failures.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: July 29, 1997
    Assignee: International Business Machines Corporation
    Inventors: James D. Bielick, Mark K. Hoffmeyer, Phillip D. Isaacs
  • Patent number: 5651713
    Abstract: The present invention provides a method for manufacturing a low voltage driven field emitter array, comprising steps of forming a thin buffer layer on a silicon substrate, making a pattern with lots of silicon nitride masks on the layer, oxidizing the upper part of the substrate and forming a relatively thick oxide layer onto the substrate except the part under the nitride masks, during which the thick oxide layer upheaves the edges of the nitride masks and extends inwardly under the nitride masks so that the edges of the thick oxide layer under the nitride masks may have a kind of bird's beak shape in cross section, etching away the nitride mask pattern, exposing the silicon substrate for the circular parts surrounded by the bird's beak shape edges by etching away the thin buffer layer, etching away the exposed substrate for making gate holes of undercut shape, and forming metal layers on the substrate and the bottom of the gate holes by evaporating a matalic evaporant downwardly and vertically against the s
    Type: Grant
    Filed: October 5, 1995
    Date of Patent: July 29, 1997
    Assignees: Korea Information & Communication Co., Ltd., Jong Duk Lee
    Inventors: Jong Duk Lee, Cheon Kyu Lee, Ho Young An
  • Patent number: 5649662
    Abstract: In this method a short pipe element (2) with a radially outwards directed bead (3) at its end rim (4) is inserted into a pipe, and a radially outwards directed bead (7, 8) is rolled in the other end (5) of the pipe element (2) and in the pipe (1), such that the pipe element is fixed inside the pipe. The pipe element (2) may before insertion into the pipe be provided with at least two radially outwards directed beads (9, 10), causing the pipe element after insertion to be tightly clamped and fixed inside the pipe, and the pipe element (2) may over a part of its outer surface be coated with a sealing material (13).
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: July 22, 1997
    Assignee: Lindab A/S
    Inventors: Peter Krichau, Werner J. Andresen
  • Patent number: 5647425
    Abstract: A mold assembly and method for lap welding a conductor to a vertical bar or rod features two vertically split mold parts having a major parting surface in which are formed a crucible, tap hole, sleeving for the conductor and a weld chamber. An offset parting surface forms a sleeving passage for the vertical bar or rod, and a portion of the weld chamber. The offset parting surface is formed in an interfitting tongue and groove which assists in the assembly of the mold parts.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: July 15, 1997
    Assignee: Erico International Corporation
    Inventors: George W. Foutz, Richard E. Singer
  • Patent number: 5647785
    Abstract: A vertical microelectronic field emitter is formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns. The trenches are filled with dielectric and the conductor layer is formed on the dielectric to form the extraction electrodes.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: July 15, 1997
    Assignee: MCNC
    Inventors: Gary Wayne Jones, Ching-Tzong Sune
  • Patent number: 5641114
    Abstract: In a bonding station the parts of the apparatus to be bonded are retained at a thermal bias temperature at a permitted level and a thermal check valve interface is provided between the bonding location and the part of the station that would serve as a conduction heat sink, thereby thermally insulating other uninvolved parts of the structure and and confining the bonding heat to the bonding region. Such confinement reduces the dwell time that the bond must remain at the bonding temperature. The bonding station has a number of features: the parts to be bonded are maintained on a support member that is provided with a heat biasing capability that can establish the assembly at a specified temperature; a retention capability, such as the use of vacuum, is provided to maintain registration and thermal contact of the part with the support; and a thermal check valve capability is provided to control the rate of heat flow through the support member so that locallized heat is controlled in dissipation.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 24, 1997
    Assignee: International Business Machines Corporation
    Inventors: Raymond Robert Horton, Chandrasekhar Narayan, Michael Jon Palmer
  • Patent number: 5639012
    Abstract: In a compound panel welding line, the compound panels discharged from a welding machine are cooled by means of a cooling unit. In the cooling unit, the welded seam is treated with a cooling fluid, in particular a rust-preventative oil. This allows the panels to be cooled and oiled within a very short time and over a very short distance, thus substantially reducing the overall length of a welding line, and greatly facilitating the handling of the compound panels.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: June 17, 1997
    Assignee: Elpatronic AG
    Inventor: Werner Urech
  • Patent number: 5637023
    Abstract: A field emission element features an emitter which has rectangular projections at its distal end capable of readily controlling the interval between electrodes in increments as small as sub-microns, in order to reduce the voltage at which the device starts field emission at the required level and to improve emission uniformity. An emitter (2,20), a collector (3,21) and a gate (5,22) are arranged on a substrate (1), which is formed with a recess (4) in proximity to the electrodes (2,3,20,21) other than the gate (5). The gate (5) is provided in the recess (4).
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: June 10, 1997
    Assignees: Futaba Denshi Kogyo K.K., Agency of Industrial Science and Technology
    Inventors: Shigeo Itoh, Teruo Watanabe, Hisashi Nakata, Norio Nishimura, Junji Itoh, Seigo Kanemaru
  • Patent number: 5637024
    Abstract: The present invention provides a simple method of combining two plate members, using an equalizing mechanism holding one of the two plate members so that the plate member is properly preloaded and can be turned by the least necessary force, and capable of combining the two plate members so that the respective contact surfaces of the plate members are joined closely and accurately. An XY-table 701 supporting a lower holding unit 5 having a holding plate 513 holding a TFT plate 11 is lifted up by a lifting table 703 to bring the TFT plate 11 into partial contact with a color filter plate 9 held by an upper holding unit 3, and then the XY-table is lifted up further to bring the respective contact surfaces 901 and 1101 of the color filter plate 9 and the TFT plate 11 into close contact with each other while the holding plate 513 is moved along a minute square path in a horizontal plane.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: June 10, 1997
    Assignee: Sony Corporation
    Inventor: Yoshimasa Goda
  • Patent number: 5634835
    Abstract: An improved dielectric layer of an electroluminescent laminate, and method of preparation are provided. The dielectric layer is formed as a thick layer from a ceramic material to provide:a dielectric strength greater than about 1.0.times.10.sup.6 V/m;a dielectric constant such that the ratio of the dielectric constant of the dielectric material to that of the phosphor layer is greater than about 50:1;a thickness such that the ratio of the thickness of the dielectric layer to that of the phosphor layer is in the range of about 20:1 to 500:1; anda surface adjacent the phosphor layer which is compatible with the phosphor layer and sufficiently smooth that the phosphor layer illuminates generally uniformly at a given excitation voltage.The invention also provides for electrical connection of an electroluminescent laminate to voltage driving circuity with through-hole technology. The invention also extends to laser scribing the transparent conductor lines of an electroluminescent laminate.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: June 3, 1997
    Assignee: Westaim Technologies Inc.
    Inventors: Xingwei Wu, James A. R. Stiles, Ken K. Foo, Phillip Bailey
  • Patent number: 5632434
    Abstract: A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: May 27, 1997
    Assignee: Regents of the University of California
    Inventors: Leland B. Evans, Vincent Malba
  • Patent number: 5632437
    Abstract: A lid is sealed to an integrated circuit package by a method that uses a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The pressure foot is retracted against the spring bias while secondary jig index pins are meshed with corresponding sockets in the fabrication boat that are aligned with the package position on the boat. When the pins and sockets are meshed, the pressure foot is released to apply optimal assembly force at the package center normal of the package lid plane.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: May 27, 1997
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Mirek Boruta, Galen Kirkpatrick
  • Patent number: 5632664
    Abstract: A field emission device cathode (10) may be fabricated by forming a dielectric layer (14) on an upper surface of a resistive layer (12). A gate layer (16) is formed on the dielectric layer (14). An opening is formed in the gate layer (16) and a microtip cavity (18) is formed in the dielectric layer (14). The microtip cavity (18) extends through the opening in the gate layer (16) to the resistive layer (12). A conductive layer is formed on the gate layer (16) and the resistive layer (12) within the microtip cavity (18) to form a conductive opening layer (20) on the gate layer (16) and a microtip cavity layer (22) on the resistive layer (12).
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: May 27, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: John W. Scoggan, Edward C. Lee
  • Patent number: 5628661
    Abstract: A method is provided for fabricating a field emission device which can be adopted as the source for a flat panel display, an ultra-high frequency amplifier sensor, or an electron-beam-applied instrument. A polyimide layer is used as a release layer and a metal mask is formed thereon, thereby enabling the height of micro-tips to be easily controlled. Since the polyimide layer is soluble in an appropriate solvent, contamination does not occur during an etching process, thereby increasing the reliability of the device.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 13, 1997
    Assignee: Samsung Display Devices, Co., Ltd.
    Inventors: Jong-min Kim, Nam-sin Park
  • Patent number: 5628662
    Abstract: An anode plate 40, suitable for use in a field emission display tetrode, includes a transparent planar substrate 42 having thereon a layer 46 of a transparent, electrically conductive material, which comprises the anode electrode of the display tetrode. Barrier structures 48 comprising an electrically insulating, preferably opaque material, are formed on anode electrode 46 as a series of parallel ridges. Atop each barrier structure 48 are a series of electrically conductive stripes 50, which function as deflection electrodes. Luminescent material 52 overlies anode electrode 46 in the channels between barrier structures 48. Conductive stripes 50 are termed into three series such that every third stripe 50 is electrically interconnected. Deflection voltage controller 70 permits selective deflection of electrons toward the proper luminescent material 52.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: May 13, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth G. Vickers, Henry S. Yan, Kurt P. Wachtler
  • Patent number: 5628659
    Abstract: A system and method is available for fabricating a field emitter device, where in an emitter material, such as copper, is deposited over a resistive layer which has been deposited upon a substrate. Two ion beam sources are utilized. The first ion beam source is directed at a target material, such as molybdenum, for sputtering molybdenum onto the emitter material. The second ion beam source is utilized to etch the emitter material to produce cones or micro-tips. A low work function material, such as amorphous diamond, is then deposited over the micro-tips.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: May 13, 1997
    Assignees: Microelectronics and Computer Corporation, SI Diamond Technology, Incorporated
    Inventors: Chenggang Xie, Nalin Kumar, Howard K. Schmidt
  • Patent number: 5628665
    Abstract: The glove box has a rotatably supported bottom member (2, 11, 51) which is quipped with a number of product holders (14) positioned concentrically with the rotational axis of the bottom member. The product holders receive subassemblies or precursor products to be processed, partly within and partly without the glove box. Typical precursor products are discharge vessels for discharge lamps, of small size, for example having discharge vessel volumes in the tenths and hundredths of a cubic centimeter, which are to be flushed with a flushing gas, and then filled with an ionizable fill. Rotation of the bottom member delivers the products in the product holders to work-stations at which flushing, filling and other operations are carried out inside the glove box. Simultaneously, other operations such as pinching and sealing portions of the discharge vessels can be carried out outside of the glove box by suitable outwardly located operating stations (18).
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: May 13, 1997
    Assignee: Patent-Treuhand-Gesellschaft F. Elektrische Gluehlampen mbH
    Inventors: Dieter Lang, Anton Schloegl, Dieter Deckardt
  • Patent number: 5622303
    Abstract: The method and the device serve for soldering of workpieces, namely of pc boards and substrates, which are equipped with chip component parts and/or microelements and/or assemblies comprised thereof. Such boards are passed through a main solder bath or at least one main solder wave, and the workpiece is contacted with the surface of the wave. The solder wave has an imaginary break edge 2, i.e., a break edge at which the solder loses the contact with the workpiece in connection with an unwettable workpiece. The imaginary break edge 2 of the soldering device 1 extends not in a straight line and, viewed in the direction of conveyance 3, has at least one diminution 4, i.e., two edge parts ending in a point, i.e., the edges form a triangle.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: April 22, 1997
    Inventor: Rainer Worthmann