Patents Examined by Jennifer M Dolan
  • Patent number: 7459392
    Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez, Michael L. McSwiney
  • Patent number: 7439553
    Abstract: In a liquid crystal display device, a recessed portion is formed in a portion of a periphery of a lower frame, a columnar member is provided to the recessed portion, the columnar member is allowed to pass through a hole formed in a projecting portion which is provided on an optical sheet, and a side surface of a liquid crystal panel is brought into contact with the columnar member. The columnar member provided on the lower frame not only determines the position of the liquid crystal panel with respect to the lower frame, but also determines the position of the optical sheet with respect to the lower frame and firmly holds the optical sheet onto the lower frame, thus preventing the disengagement of the optical sheet from the lower frame.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: October 21, 2008
    Inventor: Norihisa Fukayama
  • Patent number: 7432132
    Abstract: A method of making efficient Integrated Diamond Carrier heat sink and mounting structures usable typically to mount the solid-state laser bars often employed for pumping high power lasers, for example. The disclosed method forms the Integrated Diamond Carrier on a shaped sacrificial substrate member by chemical vapor deposition growing of diamond on a patterned substrate, made from for example silicon semiconductor. The substrate serves as a mold and is etched away after Integrated Diamond Carrier base plate formation leaving the freestanding diamond carrier. Optically usable surfaces are achieved on the Integrated Diamond Carrier through use of substrate crystal plane characteristics and an improved deposition arrangement.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: October 7, 2008
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Shlomo Z. Rotter, Susan L. Heidger
  • Patent number: 7432118
    Abstract: A VCSEL with current confinement achieved by an oxide insulating region and by an ion implant region. An annular shaped oxide layer is formed, and a gain guide ion implant is formed. The ion implant gain guide includes a central region having high conductivity. The VCSEL further includes first and second mirrors that are separated by an optical path of at least one wavelength. Furthermore, the oxide insulating region beneficially has a optical path of less than ¼ wavelength. The ion implanted spatial region is beneficially concentrically aligned with the oxide insulating region.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: October 7, 2008
    Assignee: Finisar Corporation
    Inventors: James A. Cox, Eva Strzelecka
  • Patent number: 7432565
    Abstract: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts have portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Matthias Passlack
  • Patent number: 7429506
    Abstract: A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal contact electrode on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts having portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure an avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 30, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Matthias Passlack
  • Patent number: 7427524
    Abstract: Optoelectronic device packaging assemblies and methods of making the same are described. In one aspect, an optoelectronic device packaging assembly includes an electrical sub-mount that includes a mounting area, a device turning mount, and a light-emitting device. The device turning mount has a sub-mount mounting side that is attached to the mounting area of the electrical sub-mount and a device mounting side that has a device mounting area that is oriented in a plane that is substantially perpendicular to the mounting area of the electrical sub-mount. The light-emitting device includes one or more semiconductor layers that terminate at a common light-emitting surface and are operable to emit light from the light-emitting surface. The light-emitting device is attached to the device mounting area of the device turning mount with the light-emitting surface oriented in a plane that is substantially parallel to the mounting area of the electrical sub-mount.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: September 23, 2008
    Assignee: Avago Technologies General IP (Singapore)
    Inventors: Lawrence R. McColloch, James A. Matthews, Robert E. Wilson, Brenton A. Baugh
  • Patent number: 7416915
    Abstract: Photoelectric converters are arranged two-dimensionally in a semiconductor substrate. A planarizing layer, a light shielding film, a further planarizing layer and condenser lenses are formed sequentially on the semiconductor substrate and the photoelectric converters. The light shielding film has apertures at positions corresponding to the photoelectric conversion devices. Multilayer interference filters that transmit either a red, green or blue wavelength component of light are disposed in the apertures.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: August 26, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kasano, Yuichi Inaba, Takumi Yamaguchi
  • Patent number: 7414315
    Abstract: A semiconductor device includes a substrate, an inter-metal dielectric (IMD) layer over the substrate, and either a nitrogen-containing tetraethoxysilane (TEOS) oxide layer or an oxygen-rich TEOS oxide layer over the IMD layer. The molecular ratio of oxygen in the oxygen-rich TEOS oxide layer is greater than 70%. The IMD layer comprises an extra-low dielectric constant (ELK) layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsang-Jiuh Wu, Syun-Ming Jang
  • Patent number: 7408183
    Abstract: A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions. The semiconductor laser structure is epitaxially grown on a substrate with at least a lower cladding layer, an active layer, an upper cladding layer, and a contact layer. Dry etching through a lithographically defined mask produces a laser mesa of length lc and width bm. Another sequence of lithography and etching is used to form a ridge structure with width w on top of the mesa. The etching step also forming mirrors, or facets, on the ends of the laser waveguide structures. The length ls and width bs of the chip can be selected as convenient values equal to or longer than the waveguide length lc and mesa width bm, respectively.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: August 5, 2008
    Assignee: Binoptics Corporation
    Inventors: Alex A. Behfar, Wilfried Lenth
  • Patent number: 7408264
    Abstract: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Clément J. Fortin, Pierre M. Langevin, Son K. Tran, Michael B. Vincent
  • Patent number: 7407855
    Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: August 5, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Nagata
  • Patent number: 7397110
    Abstract: A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 ?cm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: July 8, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koji Sueoka, Shinsuke Sadamitsu
  • Patent number: 7394129
    Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: July 1, 2008
    Assignee: Siltronic AG
    Inventors: Dieter Gräf, Markus Blietz, Reinhold Wahlich, Alfred Miller, Dirk Zemke
  • Patent number: 7393709
    Abstract: The present invention provides a method for manufacturing a microlens in a semiconductor substrate having a first surface and a second surface, comprising the steps of preparing the semiconductor substrate, forming a first resist layer approximately cylindrical in form on the first surface of the semiconductor substrate, reflowing the first resist layer by heat treatment while holding the semiconductor substrate in such a manner that the first surface is normal to a vertical line and placed below the second surface, thereby to deform the first resist layer into a second resist layer approximately hemispherical in form, and simultaneously etching the second resist layer and the semiconductor substrate by means of anisotropic etching to form the corresponding lens in the semiconductor substrate.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: July 1, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Minoru Watanabe
  • Patent number: 7391059
    Abstract: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface through which emitted light passes therethrough. The interface having a dielectric function that varies spatially according to a pattern, wherein the pattern is arranged to provide light emission that has a substantially isotropic emission pattern and is more collimated than a Lambertian distribution of light.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 24, 2008
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Elefterios Lidorikis, Michael Lim, Nikolay I. Nemchuk, Jo A. Venezia
  • Patent number: 7391061
    Abstract: A light emitting diode and the method of the same are provided. The light emitting diode includes a substrate, a thermal spreading layer, a connecting layer and an epitaxial structure. The substrate is selected from a transparent substrate or a non-transparent substrate, which corresponds to different materials of the connecting layers respectively. The thermal spreading layer, configured to improve the thermal conduction of the light emitting diode, is selected from diamond, impurity-doped diamond or diamond-like materials.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Epistar Corporation
    Inventors: Yuh-Ren Shieh, Jen-Chau Wu, Chuan-Cheng Tu
  • Patent number: 7388233
    Abstract: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface including a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having a dielectric function that varies spatially according to a second pattern, wherein the second pattern is a rotation of the first pattern. A method of forming a light-emitting device is provided. The method comprises forming an interface comprising a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having a dielectric function that varies spatially according to a second pattern, wherein the second pattern is a rotation of the first pattern.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 17, 2008
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Elefterios Lidorikis, Michael Lim, Nikolay I. Nemchuck, Jo A. Venezia
  • Patent number: 7382028
    Abstract: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Heng Hsieh, Chien-Li Cheng, Yi-Shien Mor, Yung-Shun Chen
  • Patent number: 7381584
    Abstract: A CMOS image sensor and method for fabricating the same is disclosed that reconditions, repairs and/or protects a surface of a photodiode area and improves characteristics of the image sensor. The method includes forming a photodiode area and a plurality of transistors, implanting a predetermined ion into a surface of the photodiode area, and forming a surface oxide film on the surface of the photodiode area by oxidation. Therefore, it is possible to recover or repair the photodiode surface damaged during various fabrication processes, reduce or minimize surface leakage of the photodiode during subsequent processes, and improve image sensor characteristics by increasing incident light on the photodiode.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 3, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Keun Hyuk Lim