Abstract: System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput. The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.

Abstract: In a liquid crystal display device, a recessed portion is formed in a portion of a periphery of a lower frame, a columnar member is provided to the recessed portion, the columnar member is allowed to pass through a hole formed in a projecting portion which is provided on an optical sheet, and a side surface of a liquid crystal panel is brought into contact with the columnar member. The columnar member provided on the lower frame not only determines the position of the liquid crystal panel with respect to the lower frame, but also determines the position of the optical sheet with respect to the lower frame and firmly holds the optical sheet onto the lower frame, thus preventing the disengagement of the optical sheet from the lower frame.

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.

Abstract: A multi-mode integrated circuit structure. In one embodiment, an integrated circuit structure includes a first die having at least one first component disposed on a face, the first die fabricated using a first process that is optimal for operating the component in an first mode and a second die stacked on the first die, the second die having at least one second component disposed on a face and the second die fabricated using a second process separate from the first process that is optimal for operating the second component in a second mode. As such, the integrated circuit structure provides an electronic device with a single integrated circuit structure for performing operations optimally in more than one mode, such as operations in enhancement mode and operations in depletion mode.

Abstract: An optical functional film comprises a multilayer film formed by stacking a plurality of films. The plurality of films are formed by a same material and refractive indices of adjacent films are different.

Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.

Abstract: A liquid crystal display, in accordance with the present invention, includes a first substrate having a thin film transistor and a first electrode formed thereon. The first electrode is electrically connected to the thin film transistor. A first insulating layer is formed on the first substrate including the thin film transistor and the first electrode and a window is formed in the first insulating layer, the window exposing a predetermined region of the first electrode. A second electrode is provided on the first insulating layer and electrically connected to the first electrode. A second substrate includes a third electrode formed thereon. A first gap is formed between a surface of the third electrode and a surface of the predetermined region of the first electrode, and a second gap is formed between the surface of the third electrode and a surface of the second electrode. A liquid crystal layer is interposed between the first gap and the second gap.

Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.

Abstract: A method for manufacturing optically-transparent lids includes etching sub-wavelength structures on a surface of a lid wafer. The structures may be arrayed in a hexagonally closed-packed pattern.

Abstract: A method for fabricating a pattern on a substrate, includes the steps of forming banks according to formation areas of the pattern on the substrate, disposing a first function liquid between the banks, disposing a second function liquid on the first function liquid, and applying predetermined treatments to the first and the second function liquids which are disposed between the banks so as to form the pattern with plural materials stacked one on the other.

Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.

Abstract: When the laser light having the harmonic is used for crystallizing the semiconductor film, there is a problem that the energy conversion efficiency from the fundamental wave to the harmonic is low. And since the laser light converted into the harmonic has lower energy than the fundamental wave, it is difficult to enhance the throughput by enlarging the area of the beam spot. The present invention provides a laser irradiation apparatus emitting the fundamental wave simultaneously with the wavelength not longer than that of the fundamental wave, typically the harmonic converted from the fundamental wave, wherein the laser light emitted from one resonator having the fundamental wave and the wavelength not longer than that of the fundamental wave are irradiated without being separated.

Abstract: A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Abstract: A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure.

Abstract: A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.