Abstract: A backlight system (20) includes a light guide plate (220), a reflector (230) disposed below the light guide plate, and an LED (210) emitting light beams into the light guide plate. The LED includes an LED chip (213), which has a base (2131), a film layer (2132), a protecting layer (2133), and an organic layer (2134) sequentially stamped on a first electrode (212) from bottom to top. The LED chip further has an optical crystal structure including a plurality of micro-holes (2135) which run through the film layer, the protecting layer and the organic layer.

Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Abstract: A liquid crystal display device, and a fabricating method thereof, having organic pixel electrodes. The organic pixel electrodes are benefically comprised of a light sensitive organic material, preferably PEDOT (polyethylenedioxythiophene). The organic pixel electrodes are rendered electrically conductive using light. The method of fabricating a liquid crystal display device coating or screen printing a TFT substrate with the light sensitive organic material and then illuminating selected portions of the light sensitive material to form the organic pixel electrodes.

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal-paths. Other methods and apparatuses are also described.

Abstract: A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing member by pressing the pressing member against the flowable film; forming a solidified film having the first concave portion by solidifying the flowable film through annealing at a first temperature with the pressing member pressed against the flowable film; forming a burnt film having the first concave portion by burning the solidified film through annealing at a second temperature higher than the first temperature; forming a second concave portion connected at least to the first concave portion in the burnt film by forming, on the burnt film, a mask having an opening for forming the second concave portion and etching the burnt film by using the mask; and forming a plug and a metal interconnect by filing the first concave portion and the second concav

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A self-supported III-V nitride semiconductor substrate having a substantially uniform carrier concentration distribution in a surface layer existing from a top surface to a depth of at least 10 ?m is produced by growing a III-V nitride semiconductor crystal while forming a plurality of projections on a crystal growth interface at the initial or intermediate stage of crystal growth; conducting the crystal growth until recesses between the projections are buried, so that the crystal growth interface becomes flat; and continuing the crystal growth to a thickness of 10 ?m or more while keeping the crystal growth interface flat.

Abstract: A method for improving adhesion of Cu to a Ru layer in Cu metallization. The method includes providing a substrate in a process chamber of a deposition system, depositing a Ru layer on the substrate in a chemical vapor deposition process, and forming a Cu seed layer on the Ru layer to prevent oxidation of the Ru layer. The Cu seed layer is partially or completely oxidized prior to performing a Cu bulk plating process on the substrate. The oxidized portion of the Cu seed layer is substantially dissolved and removed from the substrate during interaction with a Cu plating solution, thereby forming a bulk Cu layer with good adhesion to the underlying Ru layer.

Abstract: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Abstract: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode, a gate electrode formed on the first insulating layer over the semiconductor layer, and a second insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode. The present invention provides an organic EL display manufactured with reduced mask processes which has excellent electrical characteristics and improved light transmittance.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

Abstract: A circuitry sheet (322) comprising an electronic device layer stack (304) containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method (200) that includes the steps of forming the device layer stack on a temporary substrate (300), removing material from both sides of the device layer stack, and then attaching a permanent substrate (348) to the device layer stack. The method uses one or more resist layers (600) that may be activated simultaneously and independently to impart distinct circuit pattern images (603, 608, 612) into each of a plurality of image levels (612, 616, 620) within each resist layer, thereby obviating repetitive sequential exposure, registration and alignment steps.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semiconductor device is also disclosed.

Abstract: Disclosed is a method for manufacturing an organic EL light emitting display device, comprising forming an anode electrode above a substrate, forming an organic light emitting layer above the anode electrode, performing a fluorinating treatment on a surface of the organic light emitting layer, and forming a cathode electrode directly on the fluorinated surface of the organic light emitting layer.