Patents Examined by Jennifer M Dolan
  • Semiconductor module and power conversion device
    Patent number: 7193317
    Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: March 20, 2007
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Atsuhiro Yoshizaki, Keiichi Mashino, Hiromichi Anan, Yoshitaka Ochiai
  • Method of enhancing the adhesion between photoresist layer and substrate and bumping process
    Patent number: 7189646
    Abstract: A method of enhancing the adhesion between photoresist material and a substrate that can be applied to fabricate bumps on the substrate is provided. The bump fabrication process uses at least photoresist materials each having a different viscosity. A photoresist material having a smaller viscosity, that is, a higher fluidity, is permitted to contact a passivation layer so that all the gaps on the surface of the passivation layer are completely filled and a strong bond is formed between the photoresist layer and the passivation layer. With all the gaps on the substrate completely filled, solder material is prevented from filling the gaps to form a conductive bridge between neighboring bonding pads in a subsequent bump fabrication process.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: March 13, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Min-Lung Huang
  • Organic electroluminescent device, manufacturing method therefor, and electronic devices therewith
    Patent number: 7186581
    Abstract: A method for manufacturing an organic EL device comprising: coating a composition including an organic EL material on a plurality of electrodes to form an organic EL layer on each electrode; defining an effectively optical area in which the plurality of electrodes are formed; and defining a coating area which is broader than the effectively optical area, on which the composition including an organic EL material is to be coated. According to this method, a uniform display device without uneven luminance and uneven chrominance within a pixel or among a plurality of pixels in the effectively optical area can be obtained.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: March 6, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Shunichi Seki, Katsuyuki Morii
  • Methods for treating pluralities of discrete semiconductor substrates
    Patent number: 7183208
    Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: February 27, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
  • Semiconductor device
    Patent number: 7180114
    Abstract: A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: February 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsutoshi Nakamura, Hirotaka Amakawa
  • Thermally-enhanced ball grid array package structure and method
    Patent number: 7180175
    Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: February 20, 2007
    Assignee: STMicroelectronics, Inc.
    Inventors: Tiao Zhou, Michael J. Hundt
  • Method of forming a p-type group II-VI semiconductor crystal layer on a substrate
    Patent number: 7176054
    Abstract: A method of depositing a p-type magnesium-, cadmium- and/or zinc-oxide-based II-VI Group compound semiconductor crystal layer over a substrate by a metalorganic chemical vapor deposition technique. A reaction gas is supplied to a surface of a heated substrate in a direction parallel or oblique to the substrate. The p-type magnesium-, cadmium- and/or zinc-oxide-based II-VI Group compound semiconductor crystal layer is grown on the heated substrate, while introducing a pressing gas substantially in a vertical direction toward the substrate to press the reaction gas against the entire surface of the substrate.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Cermet, Inc.
    Inventors: Jeffrey E. Nause, Joseph Owen Maciejewski, Vincente Munne, Shanthi Ganesan
  • Light emitting diode having an adhesive layer and a reflective layer and manufacturing method thereof
    Patent number: 7172909
    Abstract: A light emitting diode having an adhesive layer and a reflective layer and a manufacturing method thereof featured by adhering together a light emitting diode stack and a substrate having a reflective metal layer by use of a transparent adhesive layer so that the light rays directed to the reflective metal layer can be reflected therefrom to improve the brightness of the light emitting diode.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: February 6, 2007
    Assignee: Epistar Corporation
    Inventors: Wen-Huang Liu, Tzu-Feng Tseng, Min-Hsun Hsieh, Ting-Wei Yeh, Jen-Shui Wang
  • Method and structure for forming an integrated spatial light modulator
    Patent number: 7172921
    Abstract: A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface, processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes, and depositing a standoff layer on the electrode layer. The method further includes forming standoff structures from the standoff layer and joining the bonding surface of the first substrate to the standoff structures on the device substrate. In a particular embodiment, the method further includes, after the step of depositing a standoff layer, performing chemical mechanical polishing of the standoff layer to planarize an upper surface of the standoff layer.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: February 6, 2007
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, Dongmin Chen
  • Semi-solid metal injection methods for electronic assembly thermal interface
    Patent number: 7169650
    Abstract: To accommodate high power densities associated with high performance integrated circuits, an integrated circuit package includes a heat-dissipating structure in which heat is dissipated from a surface of a die to an integrated heat spreader (IHS) through a high capacity thermal interface formed of metal that has been injected in a semi-solid state. In one embodiment, vacuum and a shear-controlled viscosity enable semi-solid metallic material to fill a narrow chamber between the die surface and a specially shaped mold plate that doubles as an IHS, without inducing voids in the solidified metal. In another embodiment, an injection machine is disclosed. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Agostino C. Rinella, Paul A. Koning
  • Semiconductor device and method for fabricating the same
    Patent number: 7170110
    Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
  • Anodic bonding method and electronic device having anodic bonding structure
    Patent number: 7153758
    Abstract: In anodic bonding between a conductor or semiconductor and glass, in order to attain good adhesion at a lower bonding temperature than usual and improve the toughness at its boundary to obtain higher reliability for a bonded portion even in a case where bonded members are warped or dust is present at the bonding boundary, a soft metal film is formed on the surface of a conductor or semiconductor on which an active metal film having high reactivity with oxygen is formed, whereby a warp or dust, if any, can be absorbed by the deformation of the soft metal film, thereby to improve the adhesion at the boundary. Adhesion at the bonding boundary is improved even at a low bonding temperature of, e.g., about 200° C. Further, the toughness at the bonding boundary can be improved to increase reliability by roughening the bonded surface on the side of the glass.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: December 26, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shohei Hata, Hideo Sotokawa, Hiroaki Furuichi
  • Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor
    Patent number: 7153725
    Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 26, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Tie Wang, Virgil Cotoco Ararao, Il Kwon Shim, Sheila Marie L. Alvarez
  • Method of fabricating no-lead package for semiconductor die with half-etched leadframe
    Patent number: 7153724
    Abstract: A series of grooves are etched in a leadframe to be used in fabricating a group of semiconductor packages at locations where the leadframe will later be sawed to separate the semiconductor packages. In variations of the process, the grooves may be wider or narrower than the kerf of the saw cuts and may be formed on the side of the leadframe facing towards or away from the entry of the saw blade.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: December 26, 2006
    Assignee: NS Electronics Bangkok (1993) Ltd.
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai, Sitta Jewjaitham, Yee Heong Chua
  • Underfilling process in a molded matrix array package using flow front modifying solder resist
    Patent number: 7151014
    Abstract: Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By separating the top flow front and the bottom flow front, this process prevents the top flow front from wrapping around the sides of the substrates and trapping air below each substrate and in front of the bottom flow front.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Saravanan Krishnan, Choong Kooi Chee
  • Semiconductor chip package
    Patent number: 7151308
    Abstract: A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: December 19, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Shih Chang Lee
  • Memory structure and method making
    Patent number: 7148088
    Abstract: A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew L Van Brocklin, Peter Fricke
  • Surface structured light-emitting diode with improved current coupling
    Patent number: 7135709
    Abstract: Structured-surface light-emitting diode having a light generating layer and a relatively thick, transparent current-spreading layer, vertical structuring of the top surface of the current-spreading layer serves to improve the decoupling of light, while at the same time, a second electrical contact layer with a distributed, lateral structure operates to achieve substantially uniform coupling of electrical current into the current-spreading layer.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: November 14, 2006
    Assignee: Osram GmbH
    Inventors: Ralph Wirth, Klaus Streubel
  • Integrated circuit substrate material and method
    Patent number: 7135767
    Abstract: A semiconductor substrate is presented which is manufactured from hollow, gas-filled glass or ceramic microspheres, which are bound together in a dried or fired matrix. The microspheres may be glass-coated microspheres, which are bound together by sintering the outer layers of glass together. The semiconductor surface may be smoothed by glazing the surface.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: November 14, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Marvin Glenn Wong, Arthur Fong
  • Semiconductor device package and method of making the same
    Patent number: 7135765
    Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: November 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Muthiah Venkateswaran