Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.

Abstract: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode, a gate electrode formed on the first insulating layer over the semiconductor layer, and a second insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode. The present invention provides an organic EL display manufactured with reduced mask processes which has excellent electrical characteristics and improved light transmittance.

Abstract: In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained.

Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.

Abstract: A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and align to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the P-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

Abstract: A semiconductor element has an upper wiring layer and a lower wiring layer. The upper and lower wiring layers communicate with each other via a via-hole. The via-hole is filled with W. Before W is filled in the via-hole by a CVD process to connect the lower wiring layer to the upper wiring layer, a cleaning gas is supplied into the via-hole to remove particular substances, which would otherwise result in high resistance. Subsequent to the cleaning step, the W portion is formed in the via-hole. Since the high resistance substances are removed from the via-hole before the formation of the W portion, the semiconductor element (or the via-hole) has a low resistance and high reliability.

Abstract: A light-emitting diode includes a cup component, a plurality of electrical conducting traces formed on a surface of the cup component using an MID means, a light-emitting diode chip mounted on the cup component and electrically connected to at least a first and second electrical conducting trace of the plurality of electrical conducting traces, and a first connection part connected to at least the first and second electrical conducting traces for providing electrical connections to external circuitry. The light emitting diode may also include a protective element that electrically protects the light-emitting diode chip, and the connection part may include first and second leads connected electrically to the first and second electrical conducting traces, respectively. The cup component, light emitting diode chip, protective element, leads and other components may be assembled together and molded and sealed with resin.

Abstract: A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

Abstract: A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Abstract: An OLED device capable of emitting multiple colors is disclosed. In one embodiment of the invention, multiple substrates are stacked upon one another, wherein the different substrates emit light of a given color. In another embodiment of the invention, these substrates are separated by spacer particles to prevent the overlying substrates from contacting the active components.

Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal paths. Other methods and apparatuses are also described.

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

Abstract: A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.

Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: A manufacturing method of organic flat light-emitting devices includes the following steps. First, a transparent substrate is provided, which has several microstructures on its first surface and the microstructures have a maximum height of 100 ?m from the first surface. Second, a transparent anode is formed on the second surface of the transparent substrate that is opposite to the first surface. Thirdly, at least one organic electro-luminescent layer is formed on the transparent anode. Finally, a metal cathode is formed on the organic electro-luminescent layer.