Patents Examined by Jennifer M Dolan
  • Three-dimensional memory array and method of fabrication
    Patent number: 7091529
    Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: August 15, 2006
    Assignee: Sandisk 3D LLC
    Inventors: N. Johan Knall, Mark Johnson
  • Method and apparatus for structuring electrodes for organic light-emitting display and organic light-emitting display manufactured using the method and apparatus
    Patent number: 7091125
    Abstract: A method for structuring an electrode, such as, for example, a cathode and/or an anode, for an organic light-emitting display by ablating the electrodes using a laser beam. An apparatus using the method for structuring an electrode is also provided. The laser beam is expanded to cover at least one target portion of each electrode to be ablated. A method for repairing an organic light-emitting display using the method and apparatus is also provided.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: August 15, 2006
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Humbs Werner, Schrader Thomas
  • Die bonding method and apparatus
    Patent number: 7087457
    Abstract: A die bonding method and apparatus that performs bonding position detection and bonding inspection without lowering the productivity, in which after a bonding head has bonded a semiconductor chip to an island, the bonding head is moved to a wafer to pick up a semiconductor chip and is returned to the island; and during this period, an island used for bonding inspection (that is the island on which bonding has just been performed) and an island used for position detection (that is the island on which bonding is to be done next) are imaged by a camera in the same visual field, and inspection of the bonding conditions of the island used for inspection and detection of the position of the island used for position detection are performed based on the acquired image data.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Yoshiyuki Ogata, Hisashi Arai
  • Optical semiconductor device and process for producing the same
    Patent number: 7083995
    Abstract: A resist is coated on a substrate. The resist is exposed to a pattern of a plurality of diffraction gratings for setting pitches corresponding respectively to oscillation wavelengths for the plurality of semiconductor lasers and for setting heights of the diffraction gratings which provide an identical coupling coefficient independently of the oscillation wavelengths. The coating is etched in such a manner that the level of etching per unit time is identical. A stripe mask is patterned according to the arrangement of the diffraction gratings. A laser active layer is formed on each of the diffraction gratings by selective MOVPE growth. An electrode is formed on each of the laser active layer on its top surface and the backside of the substrate.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 1, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Yasutaka Sakata
  • Semiconductor package having thermal interface material (TIM)
    Patent number: 7081375
    Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: July 25, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Hyun Baek, Ho-Jeong Moon, Dong-Kil Shin, Yun-Hyeok Im
  • SOI structure and method of producing same
    Patent number: 7078771
    Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: July 18, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-Su Kim
  • Substrate assembly for stressed systems
    Patent number: 7067393
    Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 27, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Method for fabricating sensor devices having improved switching properties
    Patent number: 7063985
    Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: June 20, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Methods for making dual-damascene dielectric structures
    Patent number: 7060605
    Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: June 13, 2006
    Assignee: Lam Research Corporation
    Inventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
  • Surface mount package
    Patent number: 7057273
    Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: June 6, 2006
    Assignee: GEM Services, Inc.
    Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing
  • Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
    Patent number: 7056807
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Applications and methods of making nitrogen-free anti-reflective layers for semiconductor processing
    Patent number: 7052988
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free anti-reflective layer produced by this technique eliminates the mushrooming and footing problems found with conventional anti-reflective layers.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: May 30, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Ming Li, Jason Tian, Tom Mountsier, M. Ziaul Karim
  • High capacitance package substrate
    Patent number: 7053481
    Abstract: A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventor: Rajendran Nair
  • Monolithic multiple-wavelength laser device and method of fabricating the same
    Patent number: 7045810
    Abstract: A monolithic multiple-wavelength laser device includes a laser section of a first wavelength and a laser section of a second wavelength formed on a single GaAs substrate, wherein the laser section f the first wavelength includes a real guide structure, and the laser section of the second wavelength includes a loss guide structure. In such a multiple-wavelength laser device, loss in wave guiding can be reduced and operating current can be decreased, compared to a conventional device, when the first wavelength is within a wavelength band of about 780 nm and the second wavelength is within a wavelength band of about 650 nm, since the laser section of the first wavelength has the real guide structure.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 16, 2006
    Assignee: Sharp Kabushiki Kaish
    Inventor: Masaki Tatsumi
  • Device for establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate
    Patent number: 7045889
    Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Robert L. Canella
  • CMOS devices with balanced drive currents based on SiGe
    Patent number: 7033893
    Abstract: CMOS devices with balanced drive currents are formed with a PMOS transistor based on SiGe and a deposited high-k gate dielectric. Embodiments including forming a composite substrate comprising a layer of strained Si on a layer of SiGe, forming isolation regions defining a PMOS region and an NMOS region, forming a thermal oxide layer on the strained Si layer, selectively removing the thermal oxide layer and strained Si layer from the PMOS region, depositing a layer of high-k material on the layer of SiGe in the PMOS region and then forming gate electrodes in the PMOS and NMOS regions.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: April 25, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Qi Xiang
  • Via-filling material and process for fabricating semiconductor integrated circuit using the material
    Patent number: 7030007
    Abstract: A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(?O)O— or —S(?O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: April 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Teruhiko Kumada, Toshiyuki Toyoshima, Hideharu Nobutoki, Takeo Ishibashi, Yoshiharu Ono, Junjiro Sakai
  • Nanocircuit and self-correcting etching method for fabricating same
    Patent number: 7026247
    Abstract: A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Oleg Gluschenkov
  • Method and systems for dynamically controlling electromagnetic wave motion through a photonic crystal
    Patent number: 7026640
    Abstract: A dynamically controllable photonic crystal comprises at least one micro-cavity, and electrical means to induce carrier refraction in the vicinity of the micro-cavity. In the exemplary case when the photonic crystal is implemented in a semiconductor substrate, localized carrier refraction is achieved using field induced carrier injection or depletion into a carrier concentration column surrounding the micro-cavity. Preferably, if the substrate is silicon, the injection and depletion is achieved using various two or three terminal, unipolar or bipolar structures.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: April 11, 2006
    Assignee: Ramot at Tel Aviv University Ltd.
    Inventors: Menachem Nathan, Ben Zion Steinberg, Amir Boag
  • CMOS imager having on-chip ROM
    Patent number: 7023031
    Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Richard H. Tsai