Abstract: A semiconductor component includes a semiconductor die, a low k polymer layer on the die and redistribution conductors on the polymer layer. The component also includes bonding pads on the conductors with a metal stack construction that includes a conductive layer, a barrier/adhesion layer and a non-oxidizing layer. The bonding pads facilitate wire bonding to the component and the formation of reliable wire bonds on the component. A method for fabricating the component includes the steps of forming the conductors and bonding pads using electroless deposition. The component can be used to fabricate electronic assemblies such as modules, packages and printed circuit boards.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: A substrate is patterned by forming an indent region 8 in the surface 10 of a substrate 4 and depositing a liquid material onto the surface 10 at selected locations adjacent to the indent region 8. The liquid material spreads over the surface to an edge of the indent region, at which point further spreading is controlled by the effective enhancement of the contact angle of the liquid material relative to the surface as provided by the indent region.

Abstract: A monolithic electronic device includes a substrate, a semi-insulating, piezoelectric Group III-nitride epitaxial layer formed on the substrate, a pair of input and output interdigital transducers forming a surface acoustic wave device on the epitaxial layer and at least one electronic device (such as a HEMT, MESFET, JFET, MOSFET, photodiode, LED or the like) formed on the substrate. Isolation means are disclosed to electrically and acoustically isolate the electronic device from the SAW device and vice versa. In some embodiments, a trench is formed between the SAW device and the electronic device. Ion implantation is also disclosed to form a semi-insulating Group III-nitride epitaxial layer on which the SAW device may be fabricated. Absorbing and/or reflecting elements adjacent the interdigital transducers reduce unwanted reflections that may interfere with the operation of the SAW device.

Abstract: A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bonding pads to form a patterned adhesive layer, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer, and reflowing the bumps.

Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.

Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: A high density electrical interconnecting system of the present invention has at least one substrate piece and a flexible wrap-around interconnect assembly extending from a first surface of the substrate piece to a second surface of the substrate piece wherein the flexible wrap-around interconnect is disposed around an outer surface of the substrate piece.

Abstract: A method of manufacturing a semiconductor device including: providing a substrate having an insulating layer and a single crystal silicon layer formed on the insulating layer; forming a strain-inducing semiconductor layer on the single crystal silicon layer, the strain-inducing semiconductor having the lattice constant differing from the lattice constant of the single crystal silicon layer; changing the single crystal silicon layer into a strained silicon layer by matching a lattice of the single crystal silicon layer with a lattice of the strain-inducing semiconductor layer; and removing the strain-inducing semiconductor layer.

Abstract: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.

Abstract: A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Abstract: After a p-seat electrode-forming layer is laminated onto a light-transmissive electrode-forming layer, a first heating step and a second heating step are carried out for alloying the two layers. In the first heating step, heat treatment is performed at a relatively low temperature in an atmosphere containing oxygen. In the second heating step, heat treatment is performed at a relatively high temperature in an atmosphere not containing oxygen.

Abstract: An on-die termination resistor includes three transistors and a resistor. The resistor keeps at least one of the transistors from entering the saturation region and therefore improves the I-V characteristics of the termination resistor.

Abstract: This invention provides a method for producing semiconductor nanoparticles having a monodispersed distribution of particle sizes and the semiconductor nanoparticles produced by the same, which were insufficient in conventional reversed micelle methods. This method for producing semiconductor nanoparticles comprises steps of: forming semiconductor nanoparticles in the reaction field in the micelle or in the reversed micelle; and regulating the particle size of the semiconductor nanoparticles by size-selective photoetching, wherein the reaction field in the micelle or in the reversed micelle serves also as the dissolution field for ions that are produced when the semiconductor nanoparticles are subjected to size-selective photoetching. In this method, particle sizes of the semiconductor nanoparticles are regulated by adjusting the size of the dissolution field for ions and regulating the reactivity of size-selective photoetching.