Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.

Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.

Abstract: The present invention relates to an ultra-thin metal film, an ultra-thin metal multilayer film, and a method of fabricating an ultra-thin metal film or an ultra-thin metal multilayer film. The ultra-thin metal film and the ultra-thin metal multilayer film can be obtained by forming a dielectric film on a conductive base material in a film thickness that causes the significant tunneling effect between metals through the thin dielectric film, or a film thickness whereby the valence electrons and holes of the metal composing the metallic base material and the ultra-thin metal film are affected by the many-body effects, for example, in a film thickness wherein the band-gap width of said dielectric is narrowed; and the ultra-thin metal films are formed on the dielectric grown in the layer-by-layer mode by the deposition method.

Abstract: There is provided a white light illumination system including a radiation source, a first luminescent material having a peak emission wavelength of about 570 to about 620 nm, and a second luminescent material having a peak emission wavelength of about 480 to about 500 nm, which is different from the first luminescent material. The LED may be a UV LED and the luminescent materials may be a blend of two phosphors. The first phosphor may be an orange emitting Eu2+, Mn2+ doped strontium pyrophosphate, (Sr0.8Eu0.1Mn0.1)2P2O7. The second phosphor may be a blue-green emitting Eu2+ doped SAE, (Sr0.90-0.99 Eu0.01-0.1)4Al14O25. A human observer perceives the combination of the orange and the blue-green phosphor emissions as white light.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: The disclosed fabrication methodology addresses the problem of creating low-cost micro-electro-mechanical devices and systems, and, in particular, addresses the problem of delicate microstructures being damaged by the surface tension created as a wet etchant evaporates. This disclosure demonstrates a method for employing a dry plasma etch process to release encapsulated microelectromechanical components.

Abstract: Methods for compensating for a test temperature deviation in a semiconductor device handler are provided, in which a test temperature deviation of a semiconductor device caused by heat produced by the semiconductor device itself during testing of the semiconductor device at a preset temperature is compensated for. This allows a test of the semiconductor device to be carried out at an exact temperature.

Abstract: A photosensitive resin applied onto a substrate is exposed using a mask. In this exposure step, by appropriately setting the size of each light transmitting portion formed in the mask and an exposure gap, an exposure intensity profile on a surface of a photosensitive resin is formed so as to have an increasing and decreasing curve along the surface thereof. When the exposure is performed in accordance with the exposure intensity profile, followed by development, a resin layer having surface irregularities is formed. Subsequently, a reflection layer made of a metal thin film or the like is formed on this resin layer.

Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.

Abstract: A light emitting device containing an array of directional emission LEDs is provided. The directional emission LEDs of the array may be substrate emitting, lateral current injection, resonant cavity LEDs mounted in a flip-chip configuration. Each LED may emit a different color of light, such that the output of the array appears white to an observer. The LED array package may contain microoptical elements, such as a diffraction grating or microprisms, integrated into the light emitting surface of the package. The microoptical elements are used to mix the light beams emitted by individual LEDs in the array.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3–10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: A process for cleaning a silicon surface. First, a silicon surface is cleaned with an oxidant solution. Next, the silicon surface is rinsed with HF vapor or liquid and then with the silicon surface with hydrogen water or deionized water under megasonic agitation. Finally, the silicon surface is cleaned with an oxidant solution a second time. The present inventive cleaning process can be applied in thin film transistor (TFT) fabrication and the TFT obtained has higher electron mobility.

Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.

Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Abstract: The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (12a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (

Abstract: A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in a integrated circuit and forming electrically conductive interconnect lines after formation of the tungsten plugs, wherein at least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Separate from the formation of the tungsten plugs and electrically conductive interconnect lines, a gas is introduced into a liquid. At least one electrically conductive interconnect line is then contacted with the gas introduced liquid.

Abstract: A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.

Abstract: A device for the protection of an electronic component against electrostatic discharges. The device is made in a semiconducting layer of a substrate. The semiconducting layer covers an insulating layer. The device is connected to a contact pin to protect the electric component in order to divert an electrostatic discharge. The device includes at least one Zener diode connected to the pin to be directly polarized.