Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.

Abstract: A display device including a substrate, first and second reference voltage lines, a first insulation layer is provided. The first and second reference voltage lines are disposed in a peripheral area of the substrate. The first insulation layer having a groove is disposed on the first reference voltage line. The groove extends along a first direction and exposes a contact portion of the first reference voltage line. The first insulation layer covers a first covered portion of the first reference voltage line. The second reference voltage line contacts the contact portion at the groove and has a contact surface. In a second direction, a first width W1 of the contact surface, a second width W2 of the first reference voltage line and a third width W3 of the first covered portion are complied with 1 ?m?W1?(W2?W3), wherein than 0 and smaller than W2.

Abstract: A light-emitting device according to an embodiment includes a light-emitting part and an external wiring. The light-emitting part includes: a pair of insulating substrates that has light transmissive property and flexibility; a plurality of light-emitting elements arranged between the pair of insulating substrates; an internal wiring pattern that is provided between the pair of insulating substrates, and is connected to the light-emitting elements; and a resin layer that has light transmissive property and insulating property, and is provided between the pair of insulating substrates. An end of the external wiring is divided into a plurality of wirings having a line width that is narrower than a line width of the internal wiring pattern. An end of the internal wiring pattern is bonded, at an end of the insulating substrates, to the end of the external wiring that is divided into a plurality of wirings by an anisotropic conductive adhesive.

Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A display apparatus includes a light-source substrate portion which generates light; and a color control portion to which the generated light from the light-source substrate portion is incident and at which color of the generated light is adjusted to define a color-converted light having a color different from that of the generated light. The color control portion includes: an exit surface through which the color-converted light exits the color control portion; a substrate including a plurality of concave portions defined therein, each of the concave portions extended along a direction from the light-source substrate portion to the exit surface of the color control portion; and a plurality of color conversion members respectively in the plurality of concave portions, the color conversion members each including a color-converting material which converts the color of the generated light to the color of the color-converted light.

Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.

Abstract: A detecting device is provided. The detecting device includes a substrate, at least one transistor, at least one detecting element, and a scintillator layer. The transistor is disposed on the substrate. The detecting element is disposed on the transistor and electrically connects to the transistor. The detecting element includes a first electrode layer, a semiconductor layer, and a second electrode layer. The semiconductor layer is disposed on the first electrode layer, and the second electrode layer is disposed on the semiconductor layer. The scintillator layer is disposed on one side of the substrate, wherein at least one corner area of the scintillator layer has a curved structure or a chamfered structure.

Abstract: A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.

Abstract: Provided are acetylide-based compounds and methods of making the same. Also provided are methods of using said compounds in film deposition processes to deposit films comprising silicon. Certain methods comprise exposing a substrate surface to a acetylide-based precursor and a reactant in various combinations.

Abstract: A method for producing a solar cell, which produces a single-crystal silicon solar cell by using a single-crystal silicon substrate, including: a high-temperature heat treatment process in which the single-crystal silicon substrate is subjected to heat treatment at 800° C. or higher and 1200° C. or lower, wherein the high-temperature heat treatment process includes a conveying step of loading the single-crystal silicon substrate into a heat treatment apparatus, a heating step of heating the single-crystal silicon substrate, a temperature keeping step of keeping the single-crystal silicon substrate at a predetermined temperature of 800° C. or higher and 1200° C. or lower, and a cooling step of cooling the single-crystal silicon substrate, and, in the high-temperature heat treatment process, the length of time during which the temperature of the single-crystal silicon substrate is 400° C. or higher and 650° C. or lower is set at 5 minutes or less throughout the conveying step and the heating step.

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide and/or silicon nitride are described. Certain embodiments relate to the formation of fin-etched substrates. Other embodiments relate to the removal of source drain caps from substrates. Further embodiments relate to the processing of substrates comprising vias and/or metal contacts with bottom etch stop layers and/or liner layers.

Abstract: Reversible (relatively weak) anodic bonds permit glass and silicon components to be separated without damaging the components so that they can be reused. To this end, chamfered glass with high aluminum content can be used during the original anodic bonding. Anodic bonding is terminated after complete intimate contact is achieved and while the bond is reversible. The high aluminum content impedes further bond strengthening so that the bond does not become non-reversible via contact bonding. The chamfer provides access near the glass-silicon interface for prying the glass off the silicon to effect debonding without damaging the glass or the silicon. Accordingly, the glass, the silicon, or both may be rebounded (rather than being wastefully disposed).

Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

Abstract: Achieving high spatial resolution in contact sensing for robotic manipulation often comes at the price of increased complexity in fabrication and integration. One traditional approach is to fabricate a large number of taxels, each delivering an individual, isolated response to a stimulus. The proposed sensors include a continuous volume of soft material, e.g., a transparent polymer, and light emitting diodes configured to emit light into the transparent volume that can be received by photodetectors. The location and depth of indentations can be measured between all pairs of light emitting diodes and photodetectors in the set, and this rich signal set can contain the information needed to pinpoint contact location with high accuracy using regression algorithms.

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract: Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a display area; an edge area; a bent portion between the display area and the edge area, the edge area being bent at a predetermined angle towards a side facing away from a display surface of the display area by means of the bent portion; and a row driving circuit in the edge area.

Abstract: Techniques are described to limit heat transfer from a first electronic component to a second electronic such as by having an aperture in a lid over the second electronic component to form a gap in the conductance of heat from the first electronic component to the second electronic component. A semiconductor electronic package includes a substrate, a first electronic component that is of a first type and that is mounted along a surface of the substrate, a second electronic component that is of a second type different than the first type and that is mounted along the surface of the substrate, and a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed.

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Abstract: A method for making photocapacitor is provided. The method includes: preparing a perovskite solar cell, preparing a first supercapacitor electrode, deposing the first supercapacitor electrode onto the perovskite solar cell, dissolving a portion of a cell packaging structure and a first material, and preparing a second supercapacitor electrode opposite to the first supercapacitor electrode.