Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el

Abstract: A luminescent panel includes an upper sealing layer, a lower sealing layer, and an organic electroluminescent layer. The organic electroluminescent layer is provided between the upper sealing layer and the lower sealing layer and includes one or a plurality of organic electroluminescent elements. At least one of the upper sealing layer or the lower sealing layer includes one or a plurality of inorganic sealing films each provided with a plurality of fracture control parts. The fracture control parts each include an inorganic material having relatively lower mechanical strength than parts of the one or plurality of inorganic sealing films other than the fracture control parts.

Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.

Abstract: A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by physical vapor deposition on the backside of the bowed semiconductor substrate in regions to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve sputtering material onto a backside of a substrate using a shadow mask or by using more than one target and rotating the semiconductor substrate being sputtering operations.

Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.

Abstract: A display device including a display panel having a display area and a non-display area, the non-display area being disposed at a peripheral portion of the display area and having a bending area; an integrated circuit (IC) disposed in the non-display area to drive the display panel; a first layer formed between the display area and the IC and covering the bending area; and a first member covering the IC and the first layer and overlapping with the bending area.

Abstract: A display panel, a flexible circuit board and a display device are provided. The display panel includes a substrate, and at least one row of a plurality of input pads including at least one first-input pad disposed in the middle of the input pads and a plurality of second-input pads disposed on both sides of the first input pad. Each input pad includes a first end and a second end that are oppositely disposed, and a spacing between any adjacent two input pads includes a first spacing between adjacent two first ends and a second spacing between adjacent two second ends. The first spacing and the second spacing between any adjacent two second-input pads are not equal. Along a direction from the first-input pad to the second-input pad, starting from adjacent first-input and second-input pads, the first spacing and the second spacing successively and gradually increases, respectively.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.

Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.

Abstract: Techniques are described to limit heat transfer from a first electronic component to a second electronic such as by having an aperture in a lid over the second electronic component to form a gap in the conductance of heat from the first electronic component to the second electronic component. A semiconductor electronic package includes a substrate, a first electronic component that is of a first type and that is mounted along a surface of the substrate, a second electronic component that is of a second type different than the first type and that is mounted along the surface of the substrate, and a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion, and the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other. The method includes forming a layer over the first overlay grating. The layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion.

Abstract: Proposed is a method for manufacturing a selective emitter using a surface structure, the method includes: preparing a wafer; forming fine first surface unevenness in each of front and rear faces of the wafer; forming a texturing-inhibiting film on each of the front and rear faces of the wafer; partially patterning the front texturing-inhibiting film to expose a portion of the front face of the wafer; forming second surface unevenness in the exposed portion of the wafer, wherein the second surface unevenness has a roughness greater and deeper than a roughness of the first surface unevenness; removing the texturing-inhibiting films; and forming a selective emitter on a surface of the wafer having the first surface unevenness and the second surface unevenness defined therein using a doping process.

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.

Abstract: Provided relates to a method for manufacturing an anisotropic conductive adhesive and a method for mounting a component using an anisotropic conductive adhesive, and provides a method for manufacturing an anisotropic conductive adhesive, including: a process of removing a first oxide film on solder particles by using a first reducing agent; and a process of manufacturing an anisotropic conductive adhesive by mixing the solder particles, a gapper, and an adhesive resin.

Abstract: A display substrate includes a first conductive line extending along a first direction and a second conductive line partially overlapping the first conductive line with a first insulation layer in between. The second conductive line includes a first substantially linear portion and a second substantially linear portion extending along the first direction, and an angled portion disposed between the first substantially linear portion and the second substantially linear portion. At least one side surface of the angled portion extends along a second direction intersecting the first direction.

Abstract: Provided is an active matrix substrate that includes a thin film transistor that has a first semiconductor layer and an ESD protection circuit. The ESD protection circuit includes a diode element. The diode element has a first electrode in a gate metal layer, a second semiconductor layer that overlaps a first electrode, and a second electrode and a third electrode electrically connected to a second semiconductor layer in a source metal layer. First and second electrodes of the diode element are electrically connected. The ESD protection circuit further includes a reserve diode structure. The reserve diode structure includes a fourth electrode in the gate metal layer and is in an electrically floating state, and a third semiconductor layer that is formed in the same layer as the first and second semiconductor layers and overlaps the fourth electrode with an insulation layer in between.

Abstract: A semiconductor device package includes a circuit layer, an electronic component, an electronic component, a first passivation layer and a second passivation layer. The circuit layer has a first surface. The electronic component is disposed on the first surface of the circuit layer. The first passivation layer is disposed on the first surface of the circuit layer. The first passivation layer has a first surface facing away the circuit layer. The second passivation layer is disposed on the first surface of the first passivation layer. The second passivation layer has a second surface facing away the circuit layer. A uniformity of the first surface of the first passivation layer is greater than a uniformity of the second surface of the second passivation layer.

Abstract: A display device includes a flexible base layer including a first portion and a second portion disposed around the second portion; a display unit disposed on a first surface of the first portion and including a light emitting element; a driving circuit disposed on a first surface of the second portion and including a driving chip; a support member attached to a second surface of the first portion and a second surface of the second portion; and an adhesive member disposed between the flexible base layer and the support member, wherein the adhesive member includes a first adhesive member having a first elastic modulus and a second adhesive member having a second elastic modulus that is higher than the first elastic modulus, and the second adhesive member overlaps the driving circuit.