Abstract: A semiconductor device includes a semiconductor substrate including a first epitaxial layer having a first surface and a second surface, a second epitaxial layer, a buried region formed across the first epitaxial layer and the second epitaxial layer, and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The first region is formed below at least the drain region. The second region has first and second ends in a channel length direction. The first end is located between the body region and the drain region in the channel length direction. The second region extends from the first end toward the second end such that the second end extends below at least the source region. An impurity concentration of the second region is greater than an impurity concentration of the first region.

Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

Abstract: A diffused field-effect transistor (FET) and a method of fabricating same are disclosed. The diffused FET is dually optimized in voltage resistance by incorporating both a trench isolation structure and a thick second oxide layer and thus has a more significantly improved breakdown voltage. With the thick second oxide layer ensuring suitable voltage resistance of the transistor device, its on-resistance can be reduced either by reducing the size of the trench isolation structure or increasing an ion dopant concentration of a drift region. As such, a good tradeoff between voltage resistance and on-resistance is achievable.

Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.

Abstract: A display device includes a resin substrate, a TFT layer, a light-emitting element, a frame region, a terminal portion, a bending portion, a plurality of frame wiring lines, and at least a one-layer inorganic film. The light-emitting element includes a metal electrode provided on a flattening film included in the TFT layer. In the bending portion, an opening is formed in at least the one-layer inorganic film. A frame flattening film is provided to fill the opening. The plurality of frame wiring lines are provided on the frame flattening film across the opening. The frame wiring line is formed of a metal material identical to the metal material of the metal electrode. The frame flattening film is formed of a resin material identical to the resin material of the flattening film.

Abstract: A method for annealing a semiconductor die is provided. Information regarding layout of the semiconductor die is received. At least one annealing orbit on the semiconductor die is obtained according to the received information. An alignment procedure is performed on a plurality of alignment marks of the semiconductor die according to the received information. The semiconductor die is positioned according to the alignment marks. A laser beam with a first laser parameter is projected onto the positioned semiconductor die along the annealing orbit, so as to anneal a first portion of the positioned semiconductor die covered by the annealing orbit. The positioned semiconductor die is partially covered by the annealing orbit.

Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.

Abstract: A display device includes an optical filter substrate including: a substrate; a first color filter on the substrate; a second color filter on the substrate, the second color filter spaced apart from the first color filter; a first color conversion element on the first color filter, the first color conversion element converting incident light into light of a first color; a second color conversion element on the second color filter, the second color conversion element converting the incident light into light of a second color; and a black matrix located between the first color conversion element and the second color conversion element, and between the first color filter and the second color filter.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: A light emitting module according to an embodiment includes a first insulation film and a second insulation film with a light transmissivity, a plurality of first double-sided light emitting elements disposed between the first insulation film and the second insulation film, and each including a pair of electrodes on one surface, a plurality of second double-sided light emitting elements disposed between the first insulation film and the second insulation film adjacent to the respective first double-sided light emitting elements, each including a pair of electrodes on one surface, and emitting different light from the first double-sided light emitting element.

Abstract: An end of a stacked-structure of conductive and insulating layers above a substrate has a staircase structure. The staircase includes a step pair. The risers of steps are opposed to each other. The step pairs are provided at different levels in the form in the staircase. First contact-plugs are provided on treads of respective steps of the first step part. A second contact-plug is provided in either an intermediate region between the first and the second steps of the step pair or the second step to extend in the stacked structure in a direction in which the conductive and insulating layers are stacked. A CMOS circuit is provided below the stacked structure and is connected to the second contact-plug. The second contact-plug is provided in either the intermediate region on which the first contact-plug is not formed or the second step on which the first contact-plug is not formed.

Abstract: An organic light-emitting display panel includes a plurality of pixel defining aperture regions each having a same shape and size. Each pixel defining aperture region is partitioned into six sub-pixel regions, the six sub-pixels has a same area defined by six boundary lines, each boundary line is a connection line running from a center point to an edge of the pixel defining aperture region. The plurality of the pixel defining aperture regions is characterized with three different colors. The six sub-pixels of any one of the pixel defining aperture regions is characterized with a same color. Two adjacent pixel defining aperture regions are characterized with different colors. Three connection lines between the center points of three adjacent pixel defining aperture regions have different colors constitute an isosceles right triangle, and three sub-pixel regions defined by the isosceles right triangle constitute one pixel unit.

Abstract: A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.

Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening within a mask formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching, and isotropically etching through the at least one opening to form at least one wafer dicing channel, including laterally etching a collection of nested trenches including trenches each having a non-circular cross-section from a first surface of the substrate to a second surface of the substrate opposite the first surface.

Abstract: An array substrate includes a base substrate including a plurality of pixel regions arranged in an array, a plurality of thin film transistors distributed within respective ones of the plurality of pixel regions, each of the thin film transistors including an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode including a first portion located in a second via, a passivation layer located on the source electrodes and the drain electrodes. The passivation layer is on the first portions of the drain electrode. A plurality of pixel electrodes are distributed within respective ones of the plurality of pixel regions and located on the passivation layer. Each of the pixel electrodes are electrically connected to a respective one of the drain electrodes through a respective third via that extends through the passivation layer.

Abstract: The stiffening brace may include a set of borders dimensioned to substantially surround an integrated circuit, wherein each border includes (1) a portion of material that is positioned atop a perimeter of the integrated circuit and (2) an additional portion of material that extends beyond the perimeter of the integrated circuit such that the additional portion of material overhangs a circuit board to which the integrated circuit is soldered. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.

Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a particle monitoring device for particle detection includes several capacitive micro sensors mounted on a wafer substrate to detect particles under all pressure regimes, e.g., under vacuum conditions. In an embodiment, one or more capacitive micro sensors is mounted on a wafer processing tool to measure material deposition and removal rates in real-time during the wafer fabrication process. Other embodiments are also described and claimed.

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.