Abstract: A method of controlling a power system includes receiving a signal indicative of user interaction with a handle of a removable battery, and switching a power interface of the power system from a first power sourcing mode receiving power from the removable battery to a second power sourcing mode receiving power from a back-up battery. An electronic control unit for the power system includes a memory storing computer executable instructions for controlling power sourcing in the power control system, a detector interface configured to receive a signal indicative of user interaction with a removable battery of the mobile workstation and a microprocessor configured by way of executing the computer executable instructions to switch a power interface of the power control system from a first power sourcing mode to a second power sourcing mode.

Abstract: Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided to a terminal connected in a wired or wireless network, specifically a terminal connected in a heterogeneous network, that requires TOD information. The apparatus includes a time server that provides standard TOD information, a gateway or a host personal computer (PC) that provides the standard TOD information of the time server to the terminal in a 3rd layer or lower instead of an upper layer of the open system interconnection (OSI) 7 layer model, and the terminal that adjusts a local clock according to the provided standard TOD information. According to the method and apparatus, the terminal not only maintains a very precise TOD by obtaining TOD information of the time server periodically or when required, but also obtains the TOD information without using application software for processing the TOD information.

Abstract: A power management system is disposed in a computer. The power management system includes a current detecting module and a chipset. The current detecting module is disposed between the power receiving end of an external device and the power cord of the power source of the computer for detecting the current sink by the external device and accordingly outputting a current detecting signal. The chipset adjusts the operating voltage or operating frequency of the external device according to the current detecting signal.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A power supply control apparatus communicates with a power control apparatus which controls use of electric power of an electronic apparatus. A receiver unit receives a change request to change a power supply-distribution capacity supplied to one electronic apparatus from the power control apparatus controlling use of electric power of the one electronic apparatus. A calculation unit calculates a sum of the power supply-distribution capacity supplied to the one electronic apparatus in response to the received change request and power supply-distribution capacities supplied to the other electronic apparatuses except the one electronic apparatus. A comparison unit compares the maximum power supply-distribution capacity to the sum of the calculated power supply-distribution capacities. A determination unit determines whether or not a change in the power supply-distribution capacity supplied to the one electronic apparatus is allowable based on a result of the comparison.

Abstract: A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed address in the address space. Then, if the read data satisfies a prescribed condition, an interrupt signal is generated in the polling unit. Since processor can receive the interrupt from hardware instead of performing polling with firmware, the processing burden on processor 10 can be significantly reduced.

Abstract: A method for controlling a power state of a host device, the method comprising operating a processor of a power control module integral to the host to perform operations comprising determining a current power state of the host from a plurality of possible states, receiving a remote request to alter the power state of the host device, and on the basis of the request, altering the power state of the host device from the current state to one other of the plurality of states of the host.

Abstract: Disclosed is a field device that transmits and receives data via a fieldbus in accordance with any of a plurality of communication protocols. The field device includes: a control section to give an instruction on a communication protocol to be used for transmitting or receiving data via the fieldbus; and a fieldbus controller including a transmitting and receiving section to transmit and receive data in accordance with any of the plurality of communication protocols, and a switching section to switch between the communication protocols to be used by the transmitting and receiving section based on the instruction from the control section.

Abstract: A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code.

Abstract: The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.

Abstract: The present invention discloses a power supply control device to which can be attached a number of electrical device(s), such as a computer or AV equipment. The power supply device is able to determine and monitor standby power usage levels of the device(s) so that when the control device detects that the connected electrical device(s) are not being used power supply is removed from the device(s).

Abstract: An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronized to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronization paths are provided within pointer synchronizing circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8. A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronizing path 36 when a switch in clock mode is made which requires an increase in synchronization delay.

Abstract: A portable communication apparatus is configured to perform a method for power control of a Central Processing Unit (CPU) in a portable communication apparatus. The portable communication apparatus for power control of the CPU includes a CPU configured to report an operation status of the CPU and an overhead determiner. The CPU is also configured to change a power control level according to control of the overhead determiner. The overhead determiner is configured to determine an overhead of the CPU and to control the power control level of the CPU based on the overhead of the CPU.

Abstract: Methods, including service methods, articles of manufacture, systems, articles and programmable devices are provided for adapting the power consumption of a computational device in response to environmental conditions. Operating environmental condition data relevant to the generation of electric power is acquired from an operating environment feed and analyzed to determine a high electric power demand indication. If the analyzing determines a high electric power demand indication, then a computational device automatically reduces an amount of electric power consumption.

Abstract: A system and method for enabling fallback states for energy efficient Ethernet (EEE). EEE devices can be designed to support multiple power saving states that impact layers higher than the PHY layer. Typically, these higher levels of power savings would require a greater period of time to accommodate a return to an active state. In a dynamic negotiation process, the receiving device can advertise multiple fallback power saving states to the transmitting device. The transmitting device's allocation of buffering can then determine which of the power saving states would be supported.

Abstract: A data access apparatus and a processing system using the same are disclosed herein, which can be a power-off status to permit its storage media being accessible by another processing system. When a bus signal switching and conversion unit receives a first-level control signal, the storage media is permitted to electrically connect only with a first bus channel and to perform a conversion between a first and second bus interface formats to the accessed data and to supply a system power based on a first power signal from the processing system to the storage media. When the bus signal switching and conversion unit receives the second-level control signal, the storage media is permitted to electrically connect only with a second bus channel and to perform a conversion between a second and third bus interface formats to the accessed data, and to supply a system power based on a second power signal from the another processing system to the storage media.

Abstract: A data processor includes: a data input unit that inputs data in real time; an input data storing unit in which the inputted data is stored; a signal processing unit that reads out the stored data and performs signal processing of the stored data; a signal processing control unit that has the signal processing unit intermittently perform the signal processing faster than real-time; a clock/power source control unit that reduces power consumption by restricting a clock signal and/or electric power to the signal processing unit and the signal processing control unit in an inactive period of the intermittent operation; and an input monitor unit that monitors the volume of stored data, requests the clock/power source control unit to remove a clock or power restriction based on the volume, and requests the signal processing control unit to move into an active period of the intermittent operation.

Abstract: In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Abstract: A method for operating a communications bus between a first computer and a second computer is provided. The method comprising monitoring a receiver bus coupled to the first computer for activity and confirming that the communications are determinant. The communications are confirmed by receiving a control label on the receiver bus and acknowledging to the second computer through a transmitter bus coupled to the first computer that communications are determinant. The method also comprises enabling the second computer to access data accessible by the first computer when the reliability of communications is confirmed.

Abstract: A KVM switch of universal input and programmable USB hub includes a main control unit (MCU) chip and a switching control method are disclosed. The KVM switch has a MCU circuit for controlling functions of the KVM switch, complete reports of console I/O devices, reading and corresponding transmissions of descriptors; a console device interface chip connected to the MCU; a console port, connected to the console device interface chip; a computer interface chip, connected to the MCU; a re-assignment USB hub chip, connected to the computer interface chip; and a computer port, connected to the re-assignment USB hub chip. Console USB I/O interfaces become dynamic and universal, such that the console I/O devices connected to the control port correspond to the computer port to provide full compatibility, and the console ports can be connected to various console I/O devices without any limitation of device types.