Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: A method for establishing an interface between a host and a plurality of memory devices of a system that utilizes a Multimedia Card (MMC) or Digital (SD) protocol according to an interleaving scheme. A host sequentially transmits a first sequence of commands and data to a system bus in order to allow a first memory device among the memory devices to perform a first operation. The host then transmits a second sequence of commands and data to the system bus to allow a second memory device among the memory devices to perform a second operation after transmitting the first sequence of commands and data.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SAS standard and causing communication between one or more hosts and a SATA/SAS device. The communication system includes a multi-port bridge device including two or more SAS ports through which the bridge device communicates to hosts. The multi-port bridge device further includes a SATA port through which the bridge device communicates to a SATA device, each said SAS ports having associated therewith addresses for identifying the ports, the bridge device operative to generate addresses unique to each SAS port and operative to communicate the port addresses, through a SAS frame, wherein identification of SAS ports is achievable even when the SATA device is inoperational.

Abstract: A method and system of controlling data transfer speed of bus transactions. At least some of the illustrative embodiments are methods comprising analyzing of a characteristic a first bus transaction that has yet to be applied to a bus, setting a first data transfer speed across the bus based on the characteristic of the first bus transaction, and sending the first bus transaction across the bus at the first data transfer speed.

Abstract: Methods and apparatus for adding an autonomous controller to an existing architecture such as by way of example, portable devices such as cell phones, MP3 players, and digital cameras. A circuit interposed between the memory card and the system controller of the device is controllable to couple the memory card to the system controller, or to couple the memory card to a high speed I/O controller on the circuit. When the memory card is coupled to the high speed I/O controller on the circuit, the circuit provides signals to the system controller indicative of a memory card removal event. In systems having an I/O connection such as a USB connection, the circuit also disconnects that connection from the system controller, provides signals to the system control indicative of a USB disconnect and connects the I/O connection to the memory card through a high speed data transfer unit to provide a higher speed I/O capability. Various features and capabilities are disclosed.

Abstract: A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

Abstract: A communication control apparatus for common bus connection devices is provided between a plurality of devices to which addresses are allocated and a common bus and controlling an access between each of the plurality of devices and the common bus, the communication control apparatus includes: an input determination unit configured to recognize an identification signal indicating the beginning and end of a packet for the common bus which is an information unit capable of being transmitted by one transfer operation through the common bus and determining whether or not there is an input from the common bus to the device in question, a transmission determination unit configured to determine whether or not there is a transmission of the packet from the device in question on the common bus to the common bus, and an access suspend unit configured to determine that another device on the common bus is performing a packet operation and suspending a clock in each unit in the device in question when the input determinati

Abstract: A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issued to recipient elements, and a communication channel shared amongst those processing elements over which the messages are routed. Arbitration circuitry performs an arbitration process to arbitrate between multiple messages routed over the communication channel. Each processing element issues progress data for the process executing on that processing element, the progress data indicating latency implications for the process. Arbitration control circuitry is then responsive to the progress data from each processing element to perform a priority ordering process taking into account the latency implications of each process as indicated by the progress data in order to generate priority ordering data.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.

Abstract: Embodiments of the present disclosure provide techniques for dynamically turning off bus signals driven into a graphics processing unit (GPU) when the GPU is in a low power state. The GPU may be located on a graphics card mounted to a motherboard by a bus, such as a PCI-Express bus.

Abstract: A method for addressing multiple instances of a same type of slave device on a bus is provided that includes receiving a plurality of unique device addresses at each of the slave devices and overwriting a default device address in each of the slave devices with a different one of the unique device addresses.

Abstract: Systems, methods, apparatus and software can implement a multipathing driver using dynamically loadable device policy modules that provide device specific functionality for providing at least one of input/output (I/O) operation scheduling, path selection, and I/O operation error analysis. Because the device policy modules include device specific functionality, various different devices from different manufacturers can be more efficiently and robustly supported.

Abstract: A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.

Abstract: Embodiments of a module and backplane are presented herein.

Abstract: A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

Abstract: Use of a control unit with PCI bus and SCSI bus with program equipment for the electronic semiconductor disk of a computing system. The electronic semiconductor disk includes a processor and semiconductor memory, selected from a group comprising dynamic memory, synchronous dynamic memory, static memory and flash type memory. A computing system with electronic semiconductor disk with processor, where this processor is connected by a PCI bus to a PCI adapter, which is linked through the PCI bus to a semiconductor memory, connected by the local bus to a processor. The PCI adapter comprises a unit of the programmable SCSI control unit, connected both to the interface of the PCI bus for communicating with the electronic semiconductor disk, and to the interface of the SCSI bus for communicating with the external computing system with the SCSI control unit.

Abstract: A resource interconnect architecture and associated descriptor protocol provides more efficient communication between different resources in a data processing system. One embodiment uses a backdoor interconnect that allows some resources to communicate without using a central resource interconnect. Another embodiment uses nested descriptors that allow operations by different resources to be chained together without having to communicate back to an originating descriptor resource. In another embodiment, the descriptors are generated in hardware or in software. Other embodiments assign priority or privilege values to the descriptors that optimize processing and error handling performance.

Abstract: When receiving a write message associated with data, an input/output controller issues a write-request message to a home processor node which holds the data in a memory. When receiving the write-request message, a memory controller in the processor node executes a consistency process on the basis of information, regarding the state of the data, stored in a directory, and sends a write-permission message to the input/output controller which has issued the write-request message. In response to the received write-permission message, the input/output controller in an input/output node issues an update message, serving as a write message, to the home processor node. In response to the received update message, the memory controller in the process node updates the data in the main memory. In the above process, when receiving a plurality of write messages from input/output devices, the input/output controller issues write-request messages irrespective of the progress of a preceding write message.