Abstract: In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

Abstract: A radio communication apparatus configured to perform radio communication according to a first radio communication protocol includes an identification information memory unit configured to store first identification information identifying a host apparatus and second identification information identifying the host apparatus based on a second radio communication protocol, the first and second identification information being associated with each other; an identification information reception unit; an identification information acquisition unit; and a connection request transmission unit.

Abstract: A card adapter includes a first memory card interface configured to be connected to a first memory card. The first memory card is associated with a first file system. The card adapter includes a second memory card interface that is configured to be connected to a second memory card. The second memory card is associated with a second file system. The card adapter also includes a host interface configured to connect to a host. The card adapter includes a controller operatively interposed between the first and second memory card interfaces and the host interface. The controller is configured to control the first memory card interface and the second memory card interface to control connections between each memory card that is connected thereto with the host. The controller is also configured to operate in each of two selectable modes. In a first mode the controller is operative to emulate a virtual file system that presents to the host the first file system and the second file system as a unified image.

Abstract: A system includes a minicard host connector and an open NAND flash interface host connector. The minicard host connector is configured to receive a minicard. The open NAND flash interface host connector is in physical communication with the minicard host connector and configured to receive an open NAND flash interface card. The open NAND flash interface host connector includes first and second retention arms extending from opposite ends of the open NAND flash interface host connector. The open NAND flash interface host connector is sufficiently wide for the minicard host connector to fit between the first and second retention arms.

Abstract: Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.

Abstract: A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. Multiple data transfer is provided in parallel between multiple processor cores or multiple functional units and register banks with a dynamic configuration. A low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity, and a simplified circuit is thus obtained.

Abstract: An apparatus for connecting electronic devices having a flexible cable bus housing containing a plurality of same or different communication and power channels extending along a length thereof and a plurality of bus ports at different locations along the bus housing length. Each bus port is capable of being operatively connected to one of the communication or power channels. The apparatus further includes a plurality of device connectors adapted to connect to a bus port at one end thereof and to a discrete device at another end thereof. Each connector at the device end has a different plug conforming to one of the communication or power channels. The apparatus preferably further includes a switch for connecting each bus port to the communication or power channel conforming to the device end plug when a device connector is connected to the bus port on the bus housing.

Abstract: Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Abstract: A memory card reader is disclosed that includes a memory card slot adapted to allow insertion and extraction of a memory card, a universal serial bus port, and a communication controller adapted for electrical communication with a memory card in the memory card slot and the universal serial bus port. The communication controller is responsive to a command message received in a command descriptor packet at the universal serial bus port to query the memory card in the memory card slot for information uniquely identifying the memory card. The communication controller is further adapted to generate an information descriptor packet including information uniquely identifying the memory card for provision at the universal serial bus port.

Abstract: Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port.

Abstract: Provided is a data transfer apparatus having a system bus interface 20 connected to an MC 51, a high-speed I/O bus interface connected to a high-speed I/O bus switch 54, a history selection controller 10 that selects part of transmission/reception data transferred between the MC 51 and high-speed I/O bus switch 54, a buffer section 11 that is connected to the history selection controller 10 and retains the part of the transmission/reception data selected by the history selection controller 10, and a low-speed bus interface that outputs the part of the transmission/reception data retained by the buffer section 11 to an observation apparatus 200.

Abstract: A connectivity hub enabling multiple peripheral devices to be connected with a computer includes a stationary base station functioning as a connectivity hub and a removable connectivity hub functioning by itself as a travel connectivity hub. The removable travel hub can be plugged into the stationary base station by connecting an upstream port of the removable hub to a downstream port of the base station. Thus, a user of the connectivity hub achieves the functionality of a full-featured connectivity base station as well as that of a small, easily transportable travel hub without having to purchase multiple units.

Abstract: A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.

Abstract: The invention provides a motherboard and an interface control method of a memory slot thereof. The motherboard includes a plurality of slot groups, a bus, and an interface controller. Each of the slot groups includes a first memory slot and a second memory slot connected with the bus. The first memory slot and the second memory slot form two different access addresses. The interface controller transmits a plurality of pin control signals to the corresponding slot groups to make the two access addresses of the first memory slot and the second memory slot of a using slot group of the slot groups different from the two access addresses of the first memory slot and the second memory slot of each of the other slot groups. Then, the interface controller accesses the using slot group via the bus.

Abstract: In some embodiments, a system comprises a system memory module and an access card. The system memory module connects to a memory bus on a motherboard for a personal computer, while the access card connects to an expansion bus. The access card couples to the system memory module to provide power when the personal computer is unpowered. When the personal computer boots, the system memory module operates in a cloaked mode that hides the system memory module from a memory bus. The access card switches the system memory module from the cloaked mode to a normal mode in response to a command received via the expansion bus. For long-term power outages, the access card may copy data from the system memory module to a nonvolatile information storage device. Energy storage and nonvolatile information storage may be provided by a separate longevity unit that couples to the access card.

Abstract: A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component drives the bus line to its opposite state, and, when the signal takes a second binary value, binary “0”, the component does not actively drive the bus line. During arbitration, each arbitrating component writes a unique arbitrand onto the bus, and arbitration is lost by each component that writes a binary “0” when at least one other component writes a binary “1”. The components preferably do not use transition-dominant signalling when transmitting data payloads. For such traffic they actively drive the binary “0”s as well as binary “1”s.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.