Abstract: Accurate harmonic measurements on electrical power systems where the main instrument transformers are of the capacitor coupled voltage type (CVT type) is made possible by the provision of one or more current sensors (PQCS1, PQCS2). CVTs typically have a high voltage capacitor bank (CH) and a low voltage capacitor bank (CL). One or more current sensors (PQCS1, PQCS2) is/are positioned so as to measure capacitor current and from that the input voltage (Vin) of the CVT can be determined for each frequency.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is half the frequency of the first clock.

Abstract: A semiconductor test system and method for the same. A handler is capable of moving and classifying semiconductor packages, a logic tester is capable of receiving a semiconductor package from the handler, and for testing a logic component of the semiconductor package. An analog tester may be coupled to the logic tester, where the analog tester is capable of testing an analog component of the semiconductor package. An interface unit may be included for selectively outputting a logic signal to enable the analog tester.

Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. A flex strip may alternatively be disposed behind a substrate with probes.

Abstract: An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to the test position in the systems, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a signal generator which sends test signals to the IC-chips at the test position. Between the moving of the i-th chip holding subassembly and the next subassembly in the sequence, test signals are sent to the IC-chips on all N of the chip holding subassemblies such that the signals are shifted in time from one subassembly to another. Also, while the i-th chip holding subassembly is being moved, the time shifted test signals continue to be sent to the IC-chips on the remaining N?1 chip holding subassemblies.

Abstract: The electrical circuit for driving a load comprises a transistor (12;14;22) having a load current flowing therethrough, a measurement device (30,32) for determining the voltage drop across this transistor (12;14;22), a device (42) for impressing a measuring current into the transistor (12;14;22), and a device for determining the resistance value of the transistor (12;14;22) in its ON state, this resistance value being between a known maximum value (RXMAX) and a known minimum value (RXMIN). The device for determining the resistance value is provided with a measuring bridge (36) having the transistor (12;14;22) and a known reference resistor (RR) arranged in its first bridge arm (38) and having three respectively known resistors (R1,R2,R3) arranged in its second bridge arm (40).

Abstract: A method of fabricating a plurality of micro probes comprising the steps of defining the shapes of a plurality of probes as a mask, applying a photoresist to a surface of a metal foil, overlaying the mask on the metal foil, exposing the photoresist to light passed through the mask, developing the photoresist, removing a portion of the photoresist to expose a portion of the metal foil, applying an etcher to the surface of the metal foil to remove the exposed portion to produce a plurality of probes, and chemically polishing and plating the plurality of probes.

Abstract: In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the avoidance of excessive enlargement in the scale of circuitry. A pair of an integer delay generation part and a fraction delay data generation part that are components of the semiconductor device testing apparatus is provided by the same number as that of pins of each semiconductor device under test, and a waveform control part is provided by the same number as that of the semiconductor devices under test for each of the pairs. In each waveform control part are generated a set pulse and a reset pulse for generating a test pattern signal to be applied to each of pins having the same attribute of the semiconductor devices under test, thereby to generate a test pattern signal.

Abstract: A test ancillary device with data memory and an analysis section is disposed in the vicinity of a test circuit board. The data memory is divided into two memory sections such that, when digital test data are stored in one memory section, the digital test data that have already been stored in the other memory section are loaded for analysis purpose.

Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.

Abstract: A docking system (10) and method for docking a test head (16) of a device tester to a device handler. The docking system (10) has a handler plate (12) and a tester plate (14), respectively mountable to the device handler and the test head (16). The handler plate (12) has two conversion bars (18a, 18b). Each of the two conversion bars (18a,18b) has two lateral protrusions (40a,40b). The tester plate (140 has four slot mounts (26a,26b,26c,26d), each with an escalating slot (50) that is laterally oriented for respective linear engagement with the lateral protrusions (40a,40b) for the docking. The method involves making a quick alignment of the handler plate (12) to the tester plate (14) by inserting two pre-docking guide pins into (20a,20b) two pin sockets (22a,22b) and, thereafter, actuating one or both of two actuating cams (28a,28b) for the respective linear engagement.

Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage is selected to substantially minimize leakage current associated with the plurality of devices under test. Accordingly, heat dissipation is reduced during burn-in.

Abstract: A system for detecting motion and proximity by determining capacitance between a sensor and an object. The sensor includes sensing surfaces made of a thin film of electrically conductive material mounted on a non-conductive surface. In another embodiment, the sensor is a human body. The sensor senses the capacitance between a sensor's surface and an object in its vicinity and provides the capacitance to a control system that directs machine movement. Because the sensor does not require direct contact or line-of-sight with the object, a machine can be controlled before harm occurs to the object.

Abstract: A transparent conductive layer is formed under a glass substrate. A reflection preventing layer and a reflecting layer are formed on the respective surfaces of an electro-optic crystal layer. The reflection preventing layer of the electro-optic liquid crystal layer is attached to the lower surface of the transparent conductive layer by use of an adhesive layer. In this manner, the reflection preventing layer is provided between the adhesive layer and the electro-optic crystal layer.

Abstract: An apparatus for measuring an electrical property of a semiconductor wafer includes a probe having an electrically conductive tip formed at least in part of a material that is transparent to light and a probe guard disposed adjacent the electrically conductive tip. The apparatus includes a device for selectively applying a first electrical stimulus between a semiconductor wafer and the electrically conductive tip of each probe when it is positioned in spaced relation to the semiconducting material forming the semiconductor wafer, and a device for selectively applying a second electrical stimulus between the semiconductor wafer and the probe guard of each probe. A device for measuring a response of the semiconductor wafer to the electrical stimuli and for determining from the response at least one electrical property thereof is provided. A light source can be positioned to selectively emit light through the transparent material toward the semiconductor wafer.

Abstract: A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor.

Abstract: This invention provides an evaluation board for evaluating one or more aspects of a surface mount technology system. In one aspect, the evaluation board has a substrate with at least one surface. A plurality of board pad patterns, each including a plurality of board pads, is formed on the surface. The different board pad patterns may have different shaped, sized and spaced board pads, allowing the characteristics of a surface mount technology to be tested on some or all of the board pad patterns at the same time and under uniform conditions. In another aspect, the surface may have a plurality of area-filled board pads similarly allowing a surface mount technology to be tested on the various area-filled board pads.

Abstract: A circuit and method thereof for measuring leakage current are described. The circuit includes a pre-charge device subject to a first backbias voltage and a leakage test device subject to a second backbias voltage. The leakage test device is coupled to the pre-charge device. The leakage test device is biased to an off state. A differential amplifier is coupled to the pre-charge device and the leakage test device. A delay unit is coupled to the differential amplifier and to an input of the pre-charge device. The pre-charge device is turned on and off at a frequency that corresponds to said leakage current.

Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.

Abstract: A rotary chuck with indexed rotation promotes rapid rotation of a device under test and increases the productivity of a probe station on which the device is being tested. A device mounting member of a rotatable chuck is supported for rotation on a first surface of a base until a vacuum is applied drawing the device mounting member into contact with a second surface of the base and constraining the device mounting member against rotation.